HIT-Kit News, vol. 32

 

 

Dear HIT-Kit User !


Welcome to the 32nd edition of HIT-Kit NEWS our e-mail newsletter issued by the austriamicrosystems Full Service Foundry Business Unit containing news, facts and information to help you to get the best out of our design kits. In this edition you will find news about:

 

HIT-KIT TRAINING & HIGH-VOLTAGE CMOS TECHNICAL SEMINAR


IC Technology and analog mixed signal IC Design Training

austriamicrosystems offers a three day training on austriamicrosystems' process design kit ("HIT-Kit") and a half day technical seminar on austriamicrosystems' High-Voltage CMOS process ("H35"). Both seminars take place at austriamicrosystems headquarters in Unterpremstaetten/Austria:

 
 Date:  November 28 - 30, 2006
 Location:  austriamicrosystems AG
   Unterpremstaetten
   AUSTRIA

HIT-Kit Training: A three day intensive course on mixed-mode design methodology. The aim of this course is to enable designers of integrated circuits to understand the design methodology for complex mixed-mode ASICs as well as to gain insight into the austriamicrosystems design flow. This 3 day intensive course for digital, analog and mixed-signal designers is the ideal chance to experience the power of our best-in-class HIT-Kit using state-of-the-art tools from Cadence (Encounter, Assura, ...).

 

High-Voltage CMOS Technical Seminar: This half day seminar focuses on current best practices for implementing High-Voltage designs from specification to working silicon. The 0.35µm High-Voltage CMOS process will be described with cross sections and SEM micrographs. 0.35µm High-Voltage products, currently in manufacturing, will be shown with a focus on demonstrating the integration and performance capability of the technology. austriamicrosystems' DFM-enhanced reference High-Voltage design flow will be presented, which utilizes specific analog/High-Voltage DFM tools such as design and layout verification of circuit robustness, yield centering, parasitic simulation or safe operating area check.

For more detailed information, course schedule and registration please refer to the Training Course web page.

Seating for this seminar is limited, to ensure your place register now !!


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HIT-KIT UPDATES

The following updates and add-ons available for the Cadence based HIT-Kits v3.70  & v3.71 have been released recently:
 
CMOS (C35) - Assura: Support for process option C35B4M6 and for parasitic inductance extraction
SiGe-BiCMOS (S35) - Assura: Improved DRC behaviour for 5.0V process options
High-Voltage CMOS (H35) - Assura: Support for parasitic inductance extraction as well as minor improvements to DRC, LVS and RCX
High-Voltage CMOS (CXZ) - Calibre: Published most actual Calibre runsets for DRC, LVS and XRC
- PRIMLIB_HV: CDL netlisting of device csandw solved

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UPDATED DESIGN DOCUMENTS

The following design documents have been revised or newly released. Please download the updated documents from our Download Area:

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UPDATED CIRCUIT SIMULATION PARAMETERS

The following circuit simulation models for the various simulators and technologies have been updated recently:
  • H35: Eldo, HSpiceS and Spectre: Vertn1, Vertph noise parameter update
  • S35: ADS: Rpoly2c model included
  • CXZ: Eldo and Spectre: Vertn1 early voltage parameter updated

Get the current simulation models for the various technologies from our Download Area now!  

 

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NEWSFLASH


MPW Calendar 2007: austriamicrosystems further expands Multi Project Wafer Service for Foundry Customers
austriamicrosystems’ pioneered the Multi Project Wafer service concept, a cost-efficient and fast ASIC prototyping service by combining several designs from different customers onto one wafer. This successful approach, known as Multi-Project Wafer (MPW) or shuttle run, allows to share the costs for wafer and masks among a number of different customers. In 2007, austriamicrosystems offers 22 MPW runs for the technologies C35, S35, H35 and H35-EEPROM. The detailed schedule is available on our web server at http://asic.austriamicrosystems.com/cot.

 

Next HIT-Kit version: austriamicrosystems' Design Support team is currently working on a new version of the Cadence HIT-Kit. The new release will include the high performance 0.35µm process technologies C35 (CMOS), C35O (CMOS-Opto), S35 (SiGe-BiCMOS) and H35 (High-Voltage CMOS) and the 0.8µm technologies CXQ (CMOS), CXZ (High-Voltage CMOS) and BYQ (BiCMOS). The new HIT-Kit will be qualified for the latest release of Cadence design tools (including IC 6.1) and may be used within Solaris and Linux operating systems. It is planned to be released in Q1/2007.


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austriamicrosystems IN THE NEWS

October 11, 2006: austriamicrosystems Design for Manufacturability (DFM) / Design for Yield (DFY) services boost yield of your high-performance analog products
First foundry worldwide offering comprehensive DFM/DFY reference design flow for its specialty technologies. austriamicrosystems` business unit Full Service Foundry announced at the Fabless Semiconductor Association (FSA) Supplier Expo in San Jose the availability of its comprehensive DFM/DFY reference design flow for its advanced CMOS, High Voltage CMOS, High Voltage Embedded Flash and SiGe-BiCMOS process technologies. >> Press Release


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FEEDBACK


You have been reading the 32nd edition of "HIT-Kit NEWS". Feel free to distribute it to colleagues who might be interested! All previous issues of "HIT-KIT NEWS" are here. Any questions or comments? Feel free to send an email to hitkit@austriamicrosystems.com

If you do not want to receive any future HIT-Kit NEWS please send an email to hitkit@austriamicrosystems.com. Copyright (c) November 2006: by austriamicrosystems AG, A - 8141 Unterpremstaetten, Austria. All rights reserved. Product and company names mentioned herein may be registered trademarks of their respective owners.
 

 

 

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