HIT-Kit News, vol. 27

In addition to the austriamicrosystems HIT-Kits based on Cadence software, Fraunhofer offers now a preliminary version for Tanner tools for the 0.35µm High Voltage CMOS process (H35). A fully qualified version will be released in Q3/2005. The Tanner design kits are fully supported by Fraunhofer IIS and supplied without any charges or taxes.

• 0.35µm CMOS 4M (C35)
• 0.35µm HV CMOS 4M (H35) ...preliminary version
• 0.6µm CMOS 3M (CUP)
• 0.8µm CMOS 2M (CXQ)
• 0.8µm BiCMOS 2M (BYQ)

Order-Form to get a Tanner-Design-Kit.

http://www.iis.fraunhofer.de	http://www.tanner.com

About Fraunhofer IIS: The Fraunhofer Institute for Integrated Circuits (Fraunhofer IIS) is one of Europe's leading technology and vendor independent design facilities. Fraunhofer IIS develops software, microelectronic circuits, electronic equipment and systems up to turn-key industrial installations for our customers. Read more details about Fraunhofer IIS and the available design kits for Tanner tools at Fraunhofer IIS web site or contact virtual-asic@iis.fraunhofer.de for more information.

About Tanner EDA: Tanner EDA is the worldwide leader in tools for analog/mixed signal ICs and MEMS design on the Windows platform. Headquartered in Pasadena, CA, but with sales offices worldwide, Tanner EDA develops design capture, simulation, layout and verification software for analog and mixed signal ICs used in RF, optoelectronic, biomedical, power management and other diverse applications. Tanner EDA's flagship products HiPer Verify, L-Edit Pro and T-Spice Pro provide a complete high performance design flow including schematic entry, waveform probing, full-custom layout editing, place and route, LVS and DRC verification, netlist extraction and circuit simulation. Founded in 1988, Tanner EDA is a division of privately held Tanner Research, Inc., and can be found on the World Wide Web at www.tannereda.com.

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Did you know that there is a Corner Tool included in our HIT-Kit?

As Design for manufacturing (DFM) is a major concern for all analog/mixed-signal designs, austriamicrosystems provides the perfect tool to shorten simulation setup times for process corner analysis.

The HIT-Kit Corner Tool considers voltage and temperature ranges as well as manually or automatically generated process corners as input and creates a Cadence Corner Tool setup file, which is loaded on invocation.

Using the setup file the Cadence Corner Tool automatically checks circuit operations over a range of process and environment variations and performs an circuit simulation at the defined process corners.

Read more details about the Corner tool in the tutorial HIT-Kit Corner Analysis.

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The following Design Documents have been revised or newly released. Please download the updated documents from our Download Area:

• 0.35µm CMOS Noise Parameters (C35) ENG-189, Rev 2
• 0.35µm 50V CMOS Process Parameters (H35) ENG-238, Rev 3
• 0.35µm 50V CMOS Design Rules (H35) ENG-243, Rev 3
• Package List, ASSY-168, Rev 15
• Package List Details

The following circuit simulation models for the various simulators and technologies have been updated recently:

Get the current simulation models for the various technologies from our Download Area now!

Keep your HIT-Kit up to date! The following patches available for the HIT-Kits v3.60 and v3.61 have been released recently:

All HIT-Kit patch files for the various technologies are available on our Download Area.

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Next HIT-Kit version: austriamicrosystems' Design Support team is currently working on a new version of the Cadence HIT-Kit. The new release will include the high performance 0.35µm process technologies C35 (CMOS), S35 (SiGe-BiCMOS) and H35 (High Voltage CMOS) and the 0.8µm technologies CXQ (CMOS), CXZ (CMOS High Voltage) and BYQ (BiCMOS). The new HIT-Kit will be qualified for the latest release of Cadence design tools and may be used within Solaris, HP-UX and Linux operating systems. It is planned to be released in April.

Device Model Update: The status of the 0.35um process models (C35, S35, H35) has been updated according to the related process documents. Please refer to section Device Model Status. 

MPW Calendar 2005: austriamicrosystems offers 20 MPW runs (plus 4 additional runs at Fraunhofer IIS) for the technologies C35, H35, S35, C35-Opto and C35-EEPROM. The detailed schedule is available on our web server at http://asic.austriamicrosystems.com/MPW.

FSA Supplier Expo: Visit austriamicrosystems at the FSA Supplier Expo in London on May 11 - 12, 2005.

Technical Seminar: austriamicrosystems "Full Service Foundry" philosophy is to work with its customers to offer an optimal solution for first time right silicon including extended design support services. As part of this service, austriamicrosystems is pleased to announce another complimentary half day technical seminar prior to the FSA Supplier Expo about High Voltage Design Techniques and austriamicrosystems CMOS High Voltage Processes (H35). A separate invitation to this event will follow soon.

Mar. 11, 2005: austriamicrosystems launches process supporting high-speed photodiode for next generation DVD applications
Novel high-speed / high-sensitivity wafer process available to chip designers for blue laser photo detection ICs (PDICs). austriamicrosystems' business unit Full Service Foundry announced today, at the DATE conference in Munich, the availability of a new specialty wafer process with a novel photodiode for blue laser DVD Photo Detector ICs and industrial applications. >> Press Release

Mar. 07, 2005: austriamicrosystems collaborates with Cadence to address analog IC design challenges
Leading analog-specialty foundry establishing design kits and reference flow based on Cadence Virtuoso platform. austriamicrosystems’ business unit Full Service Foundry today announced a strategic alliance with Cadence Design Systems, Inc. targeting analog integrated circuit (IC) design. The companies are collaborating to enable austriamicrosystems to deliver comprehensive HIT-Kits (austriamicrosystems process design kits, or PDKs) and reference flows based on the Cadence® Virtuoso® custom design platform. By optimizing the path from design through physical implementation, this collaboration enables analog IC designers to speed silicon to market. >> Press Release

Feb. 17, 2005: austriamicrosystems further expands Multi Product Wafer Service for CMOS, High-Voltage and RF Processes for its Foundry Customers
austriamicrosystems’ business unit Full Service Foundry provides a cost-efficient and fast ASIC prototyping service by combining several designs from different customers onto one wafer. This approach, known as Multi-Project Wafer (MPW) or shuttle run, allows to share the costs for wafer and masks among a number of different customers. >> Press Release

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If you do not want to receive any future HIT-Kit NEWS please send an email to hitkit@austriamicrosystems.com . Copyright (c) April 2005: by austriamicrosystems AG, A - 8141 Unterpremstätten, Austria. All rights reserved. Product and company names mentioned herein may be registered trademarks of their respective owners.