Mentor HIT-Kit v3.71 Release Notes

v3.71 Release Notes

March 2006

This new HIT-Kit v3.71, qualified for Mentor IC-Flow 2005.1 and for the technologies

  • 0.35µm H35B3 (HV CMOS, 3-metal)
  • 0.35µm H35B4 (HV CMOS, 4-metal)

contains proven features, a variety of improvements and new extensions summarized in the following overview

 

Related Design
Documents

 

General

  • Qualified for Solaris  8/ 9 + Red Hat EL 3.0
  • Support for IC-Flow 2005.1 (patch 0321) including ICstudio and classic DA-IC and IC-Station.
  • Improved startup script ams_icstudio to run ICstudio with the correct austriamicrosystems technology setup and libraries
  • Layout verification tool Calibre 2005.1
  • Extended groups of checks that can be enabled/disabled for DRC on demand (see also IC-Station Layout & Verification Flow)
  • Improved Eldo Monte Carlo simulation models
  • Save-Operating-Area Check (SOAC) supported
  • HIT-Kit Utilities menu within DA-IC and IC-Station including all austriamicrosystems specific utilities.
  • Improved functionality to translate Eldo- to Calibre Netlists for LVS and Calibre- to Eldo Netlists for Post Layout Simulation
  • Digital Standard Cells qualified to be used within Mentor P&R tool AutoCells
  • All standard cells also supported to be used with Cadence Silicon Ensemble for P&R
 

Updates

  • Design Rules and Process Parameter documents available on
    http://asic.austriamicrosystems.com/cgi-sbin/download_area_index.cgi
  • Calibre rule files for DRC, LVS and PEX available
  • Pcells for PMOS20H, PMOS50H, PMOS50HS and NMOS50HS updated
    Update old schematics & layouts and replace with new devices!
  • Device RPOLY1 available through whole design flow as qualified device
  • Circuit Simulator models updated
  • Parasitic PNP modeled in the parasitic models
  • Synopsys, VITAL, BuildGates, TLF and Verilog libraries available
  • Circuit Simulation models corresponding to doc ENG-238
  • All primitive Devices supported throughout the complete flow
  • Improved Model selection tools added to HIT-KIT utilities menu
  • IOLIB_HV_3M and IOLIB_HV_4M updated:
    CORNER_HV error corrected DRC
    PWRCUT*  new schematics - can be LVS checked now
    probe_pad  only a copy from the IOLIB_4M

     PROTVDDGNDP_HV removed -> should be replaced by:
    RAILPROT_SUBP_HV  for non-floating logic (gnd == vsub)
    RAILPROT_SUB5P_HV  for systems with vdd-vsub up to 5V
    RAILPROT_SUB20P_HV  for systems with vdd-vsub 5V - 20V
    RAILPROT_SUB50P_HV  for systems with vdd-vsub 20V - 50V

 

  • IOLIB_ANA_HV_3M and IOLIB_ANA_HV_4M updated:
    - All cells have to be replaced by the new version!
    - All cells are capable for 2kV HBM.
    - Includes 3.3V, 5V, 20V and 50V Analog cells
     - LV (3.3V and 5V) floating analog pads:
    APRIO*  3.3V and 5V floating analog IO cells
    APWRCUT*  Power Cut Cells for 3.3V and 5V floating analog systems
    ARAILPROT_SUBP_HV ESD protection for non-floating systems
    ARAILPROT_SUB5P_HV ESD protection floating systems up to 5V
    ARAILPROT_SUB20P_HV ESD protection floating systems 5V - 20V
    ARAILPROT_SUB50P_HV ESD protection floating systems 20V - 50V
    AVDD3ALLP_HV 3.3V floating analog VDD pad
    AGND3ALLP_HV 3.3V floating analog VSS pad
    AVSUB3ALLP_HV Substrate pad for 3.3V floating systems
    AVDD5ALLP_HV 5.0V floating analog VDD pad
    AGND5ALLP_HV 5.0V floating analog VSS pad
    AVSUB5ALLP_HV Substrate pad for 5.0V floating systems

 20V Pads
IO20  20V IO pad
POWER20  20V power supply (including full ESD protection)
PP20  20V VDD pad 
VSS20  20V VSS pad
VSUB20  Substrate pad for 50V systems
PROT20_VDD20_VSS20  ESD protection between VDD20 and VSS20
PROT20_VDD20_VSUB  ESD protection between VDD20 and VSUB
PROT20_VSS20_VSUB  ESD protection between VSS20 and VSUB

 50V Pads
IO50  50V IO pad
POWER50 50V power supply (including full ESD protection)
PP50  50V VDD pad
VSS50  50V VSS pad
VSUB50  Substrate pad for 50V systems
PROT50_VDD50_VSS50  ESD protection between VDD50 and VSS50
PROT50_VDD50_VSUB  ESD protection between VDD50 and VSUB
PROT50_VSS50_VSUB  ESD protection between VSS50 and VSUB

 

Available
Libraries

 
  • PRIMLIB: Includes all primitive devices (Low-Voltage and High-Voltage Devices)
  • A_CELLS C35 library (Analog Standard Cells)
  • CORELIB C35 library (Digital Standard Cells)
  • CORELIB_3B library (3-Bus Digital Standard Cells)
  • CORELIB_HV Floating Digital Standard Cells
  • IOLIB_3M C35 library (Digital Input/Output/Bidirectional buffers & Power Pads)
  • IOLIB_4M C35 library (Digital Input/Output/Bidirectional buffers & Power Pads)
  • IOLIB_HV_3M Floating 3 Metal Digital Input/Output/Bidirectional buffers & Power Pads
  • IOLIB_HV_4M Floating 4 Metal Digital Input/Output/Bidirectional buffers & Power Pads
  • IOLIB_ANA_3M C35 library (Analog Power Supply Pads, Analog I/O Pads)
  • IOLIB_ANA_4M C35 library (Analog Power Supply Pads, Analog I/O Pads)
  • IOLIB_ANA_HV_3M High Voltage 3 Metal Analog Power Supply Pads, Analog I/O Pads for 20V and 50V
  • IOLIB_ANA_HV_4M High Voltage 4 Metal Analog Power Supply Pads, Analog I/O Pads for 20V and 50V
  • IOLIBV5_3M C35 library (Digital Input/Output/Bidirectional buffers & Power Pads; 5V Supply)
  • IOLIBV5_4M C35 library (Digital Input/Output/Bidirectional buffers & Power Pads; 5V Supply)
  • IOLIB_3B_3M C35 library (3-Bus Digital Input/Output/Bidirectional buffers & Power Pads)
  • IOLIB_3B_4M C35 library (3-Bus Digital Input/Output/Bidirectional buffers & Power Pads)
  • IOLIBC_3B_3M core-ltd. C35 library (3-Bus Digital Input/Output/Bidirectional buffers & Power Pads)
  • IOLIBC_3B_4M core-ltd. C35 library (3-Bus Digital Input/Output/Bidirectional buffers & Power Pads)
  • IOLIB_ANA_3B_3M C35 library (3-Bus Analog Power Supply Pads, Analog I/O Pads)
  • IOLIB_ANA_3B_4M C35 library (3-Bus Analog Power Supply Pads, Analog I/O Pads)
  • IOLIBC_ANA_3B_3M core-ltd.C35 library (3-Bus Analog Power Supply Pads, Analog I/O Pads)
  • IOLIBC_ANA_3B_4M core-ltd.C35 library (3-Bus Analog Power Supply Pads, Analog I/O Pads)
  • SFCLIB_H35xx: Standard Family Cells libraries
Trademarks Artist Link, ModelSim, Calibre, ICstudio, DA-IC, IC-Station, AutoCells, ADMS, Eldo, ICnet, DMGR-IC and DVE-IC are trademarks of Mentor Graphics Corporation, Silicon Ensemble is a trademark of Cadence Design Systems, Inc., Advanced Design System, RFDE and Dynamic Link are trademarks of Agilent Technologies, Inc., Cadence, the Cadence logo and First Encounter are registered trademarks, and Encounter, Assura, Cadence NCSim and BuildGates are trademarks of Cadence Design Systems, Inc., Sun and Solaris are registered trademarks of Sun Microsystems, Inc., HP-UX is a registered trademark of Hewlett-Packard Company. All other trademarks are the property of their respective owners.
Copyright (c) 2006 austriamicrosystems AG

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