HIT-Kit v3.70: Release Notes (Cadence)

This new HIT-Kit v3.70, qualified for Cadence IC 5.1.41 and for the technologies

• 0.35µm C35B3 (CMOS, 3-metal)
• 0.35µm C35B4 (CMOS, 4-metal)
• 0.35µm S35D3 (SiGe, 3-metal)
• 0.35µm S35D4 (SiGe, 4-metal)
• 0.35µm H35B3 (HV CMOS, 3-metal) -> For H35 please use only the actual HIT-Kit v3.72
• 0.35µm H35B4 (HV CMOS, 4-metal) -> For H35 please use only the actual HIT-Kit v3.72
• 0.8µm  CXQ (CMOS)
• 0.8µm  CXZ (CMOS HV)
• 0.8µm  BYQ (BiCMOS)

contains proven features, a variety of improvements and new extensions summarized in the following overview

• 0.35µm CMOS C35 Process Parameters
  Document: Eng-182
  Revision: 3.0
  09/2004
• 0.35µm CMOS C35 Design Rules
  Document: Eng-183
  Revision: 4.0
  11/2004
• 0.35µm HBT BiCMOS Process Parameters
  Document: ENG-219
  Revision: 3.0
  8/2004
• 0.35µm HBT BiCMOS Design Rules
  Document: ENG-218
  Revision: 5.0
  11/2004
• 0.35µm 50V CMOS Process Parameters
  Document: ENG-238
  Revision: 3.0
  3/2005
• 0.35µm 50V CMOS Design Rules
  Document: ENG-243
  Revision: 3.0
  11/2004

• 0.8 µm BiCMOS Process Parameters
  Document: ENG-124
  Revision: 3.0
  07/2002
• 0.8 µm BiCMOS Design Rules
  Document: 9931016
  Revision: 2.0
  04/2002
• 0.8 µm CXQ CMOS Process Parameters
  Document: 9933013
  Revision: C
  08/1999
• 0.8 µm CXQ CMOS Design Rules
  Document: 9931029
  Revision: C
  06/1999
• 0.8 µm HV CMOS Process Parameters
  Document: 9933014
  Revision: 2.0
  04/2001
• 0.8 µm HV CMOS Design Rules¹)
  Document: 9931030
  Revision: 2.0
  04/2001

• Qualified for Solaris 7/ 8/ 9 + Red Hat Linux 7.3 + Red Hat EL 3.0
• Layout verification tool Assura 3.1.4
• CDL netlisting fully supported to generate Calibre netlists
• Graphical interface for Safe-Operating-Area-Check (SOAC)
• Full Setup and support for Cadence Multipart Paths objects
• Improved Monte Carlo simulation models
• Technology specific setup files for Synopsys Synthesis, VITAL, 
  Verilog, Cadence Build Gates and TLF.
• Libraries tested and qualified for Cadence NC-Sim 5.4
  (NC-Verilog, NC-VHDL and VerilogXL) and ModelSim 6.0b
• Support for CDS AMS Designer + UltraSim
• Support for Agilent Dynamic Link
• Support for Agilent RFDE (2004A)
• Support for Mentor Artist Link
• Support for Nassda's HSIM

• Design Rules, Process Parameter and Noise Parameter documents available on asic.austriamicrosystems.com/download.
• Updated Assura rule files for DRC, LVS and RCX
• Updated Calibre rule files for DRC, LVS and EXT
• Updated Synopsys, VITAL, BuildGates, TLF and Verilog libraries
• First Encounter libraries available.
• Updated datasheets with updated values for all CORE & IOLIBs.
• Memory frontend model generation and documentation available on http://asic.austriamicrosystems.com/download
• Circuit Simulation models corresponding to document ENG-182 
• CORELIB library (Digital Standard Cells)
• CORELIB_3B library (3-Bus Digital Standard Cells)
• IOLIBC_3B_3M core-ltd. library (3-Bus Dig. Input/Output/Bidirectional buffers & Power Pads)
• IOLIBC_3B_4M core-ltd. library (3-Bus Dig. Input/Output/Bidirectional buffers & Power Pads)
• IOLIBC_ANA_3B_3M core-ltd. library (3-Bus Analog Power Supply Pads & Analog I/O Pads)
• IOLIBC_ANA_3B_4M core-ltd. library (3-Bus Analog Power Supply Pad & Analog I/O Pads)
• IOLIB_3M library (Digital Input/Output/Bidirectional buffers & Power Pads) available. 
• IOLIB_4M library (Digital Input/Output/Bidirectional buffers & Power Pads) available.
• IOLIB_3B_3M library (3-Bus Digital Input/Output/Bidirectional buffers & Power Pads) available.
• IOLIB_3B_4M library (3-Bus Digital Input/Output/Bidirectional buffers & Power Pads) available.
• IOLIBV5_3M library (Digital Input/Output/Bidirectional buffers & Power Pads; 5V Supply) available.
• IOLIBV5_4M library (Digital Input/Output/Bidirectional buffers & Power Pads; 5V Supply) available.
• IOLIB_ANA_3M library (Analog Power Supply Pads, Analog I/O Pads) available.
• IOLIB_ANA_4M library (Analog Power Supply Pads, Analog I/O Pads) available.
• IOLIB_ANA_3B_3M library (3-Bus Analog Power Supply Pads, Analog I/O Pads) available.
• IOLIB_ANA_3B_4M library (3-Bus Analog Power Supply Pads, Analog I/O Pads) available.
• A_CELLS library (Analog Standard Cells) available. 
  - New set of Bandgap references available. 
  - Analog-Digital Converter ADC8 available.
• PRIMLIB: Primitive devices
• PRIMLIBRF: RF Primitive devices fully supported throughout the complete design flow.
• SPIRALS_3M library (inductors)  available
• SPIRALS_4M library (inductors)  available
• SFCLIB_C35xx: Standard Family Cells libraries updated

• Design Rules and Process Parameter documents available on asic.austriamicrosystems.com/download
• Updated Assura rule files for DRC, LVS and RCX available.
• Updated Calibre rule files for DRC, LVS and EXT available. 
• Synopsys, VITAL, BuildGates, TLF and Verilog libraries available
• First Encounter libraries available.
• Circuit Simulation models corresponding to doc ENG-219
• CORELIB library (Digital Standard Cells)
• CORELIB_3B library (3-Bus Digital Standard Cells)
• IOLIBC_3B_3M core-ltd. library (3-Bus Dig. Input/Output/Bidirectional buffers & Power Pads)
• IOLIBC_3B_4M core-ltd. library (3-Bus Dig. Input/Output/Bidirectional buffers & Power Pads)
• IOLIBC_ANA_3B_3M core-ltd. library (3-Bus Analog Power Supply Pads & Analog I/O Pads)
• IOLIBC_ANA_3B_4M core-ltd. library (3-Bus Analog Power Supply Pad & Analog I/O Pads)
• IOLIB_3M library (Digital Input/Output/Bidirectional buffers & Power Pads)
• IOLIB_4M library (Digital Input/Output/Bidirectional buffers & Power Pads)
• IOLIB_3B_3M library (3-Bus Digital Input/Output/Bidirectional buffers & Power Pads)
• IOLIB_3B_4M library (3-Bus Digital Input/Output/Bidirectional buffers & Power Pads)
• IOLIBV5_3M library (Digital Input/Output/Bidirectional buffers & Power Pads; 5V Supply)
• IOLIBV5_4M library (Digital Input/Output/Bidirectional buffers & Power Pads; 5V Supply)
• IOLIB_ANA_3M library (Analog Power Supply Pads, Analog I/O Pads)
• IOLIB_ANA_4M library (Analog Power Supply Pads, Analog I/O Pads)
• IOLIB_ANA_3B_3M library (3-Bus Analog Power Supply Pads, Analog I/O Pads)
• IOLIB_ANA_3B_4M library (3-Bus Analog Power Supply Pads, Analog I/O Pads)

• A_CELLS library (Analog Standard Cells)
  - New set of Bandgap references available. 
  - Analog-Digital Converter ADC8 available.

• PRIMLIB: Primitive devices (new devices available according to ENG-218, rev. 3.0)
  Note: Please be aware that the "cstack" device has changed. In existing schematics there is a new placement of this device necessary in order to get correct simulation results!

• PRIMLIBRF: RF Primitive devices

• SPIRALS_3M library (inductors)

• SPIRALS_4M library (inductors)

• RFPADS_4M RF Pad Library, 4-met

• RFPADS_3B_4M RF Pad Library, 4-met, 3-Bus

• SFCLIB_S35xx: Standard Family Cells libraries updated

• Design Rules and Process Parameter documents available on asic.austriamicrosystems.com/download
• Updated Assura rule files for DRC, LVS and RCX
• Updated Calibre rule files for DRC, LVS and EXT
• Synopsys, VITAL, BuildGates, TLF and Verilog libraries
• First Encounter libraries available.
• Circuit Simulation models corresponding to doc ENG-238
• PRIMLIB: Includes all primitive devices (Low-Voltage and High-Voltage Devices)
• A_CELLS C35 library (Analog Standard Cells)
• CORELIB C35 library (Digital Standard Cells)
• CORELIB_3B library (3-Bus Digital Standard Cells)
• CORELIB_HV Floating Digital Standard Cells
• IOLIB_3M C35 library (Digital Input/Output/Bidirectional buffers & Power Pads)
• IOLIB_4M C35 library (Digital Input/Output/Bidirectional buffers & Power Pads)
• IOLIB_HV_3M Floating 3 Metal Digital Input/Output/Bidirectional buffers & Power Pads
• IOLIB_HV_4M Floating 4 Metal Digital Input/Output/Bidirectional buffers & Power Pads
• IOLIB_ANA_3M C35 library (Analog Power Supply Pads, Analog I/O Pads)
• IOLIB_ANA_4M C35 library (Analog Power Supply Pads, Analog I/O Pads)
• IOLIB_ANA_HV_3M High Voltage 3 Metal Analog Power Supply Pads, Analog I/O Pads for 20V and 50V
• IOLIB_ANA_HV_4M High Voltage 4 Metal Analog Power Supply Pads, Analog I/O Pads for 20V and 50V
• IOLIBV5_3M C35 library (Digital Input/Output/Bidirectional buffers & Power Pads; 5V Supply)
• IOLIBV5_4M C35 library (Digital Input/Output/Bidirectional buffers & Power Pads; 5V Supply)
• IOLIB_3B_3M C35 library (3-Bus Digital Input/Output/Bidirectional buffers & Power Pads)
• IOLIB_3B_4M C35 library (3-Bus Digital Input/Output/Bidirectional buffers & Power Pads)
• IOLIB_ANA_3B_3M C35 library (3-Bus Analog Power Supply Pads, Analog I/O Pads)
• IOLIB_ANA_3B_4M C35 library (3-Bus Analog Power Supply Pads, Analog I/O Pads)
• SFCLIB_H35xx: Standard Family Cells libraries

• Design Rules and Process Parameter documents available on asic.austriamicrosystems.com/download
• Updated Assura rule files for DRC, LVS and RCX available.
• Updated Calibre rule files for DRC, LVS and EXT available. 
• Updated Synopsys, VITAL, BuildGates, TLF and Verilog libraries available.
• Updated datasheets with corrected Area values for all core cells included in libraries 
  HRDLIB and HRDLIBL.
• A_CELLS_A library (Analog Standard Cells)
• HRDLIB library (Digital Core Standard Cells)
• HRDLIBL library (Digital Core Standard Cells / Low Power)
• IOLIB library (Digital Input/Output/Bidirectional buffers & Power Pads)
• IOLIB_ANA library (Analog Power Supply Pads, Analog I/O Pads)
• PRIMLIB Primitive devices
• SFCLIB_CXx: Standard Family Cells updated.

• Design Rules and Process Parameter documents available on asic.austriamicrosystems.com/download
• Updated Assura rule files for DRC, LVS and RCX available.
• Updated Calibre rule files for DRC, LVS and EXT available. 
• Updated Synopsys, VITAL, BuildGates, TLF and Verilog libraries available.
• Updated datasheets with corrected Area values for all core cells included in libraries 
  HRDLIB, HRDLIBL, HRDLIB_HV and HRDLIBL_HV.
• A_CELLS_A library (Analog Standard Cells)
• A_CELLS_HV library (Analog Standard Cells HV)
• HRDLIB library (Digital Core Standard Cells)
• HRDLIBL library (Digital Core Standard Cells / Low Power)
• HRDLIB_HV library (Digital Core Standard Cells HV)
• HRDLIBL_HV library (Digital Core Standard Cells / Low Power HV)
• IOLIB library (Digital Input/Output/Bidirectional buffers & Power Pads)
• IOLIB_ANA_HV library (Analog Power Supply Pads, Analog I/O Pads)
• IOLIB_HV library (Power Supply Pads, I/O Pads)
• PRIMLIB Primitive devices
• PRIMLIB_HV Primitive devices HV
• SFCLIB_CXx: Standard Family Cells updated.

• Design Rules and Process Parameter documents available on asic.austriamicrosystems.com/download
• Updated Assura rule files for DRC, LVS and RCX available.
• Updated Calibre rule files for DRC, LVS and EXT available. 
• Synopsys, VITAL, BuildGates, TLF and Verilog libraries available.
• Updated circuit simulation models included.
• A_CELLS library (Analog Standard Cells)
• A_CELLS_B library (BiCMOS Analog Standard Cells)
• HRDLIB library (Digital Core Standard Cells)
• HRDLIB_B library (Digital Core Standard Cells BiCMOS)
• IOLIB library (Digital Input/Output/Bidirectional buffers & Power Pads)
• IOLIB_B library (BiCMOS Digital Input/Output/Bidirectional buffers & Power Pads)
• SPIRALS library (inductors)  available
• RFPADS RF Pad Library available
• SFCLIB_BYx: Standard Family Cells updated.