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IC Station - Layout & Verification Flow

 

  • 1 Introduction & Definitions
  • 2 austriamicrosystems' Specific Data
    • 2.1 The Process-File
    • 2.2 The Library
    • 2.3 The Rule-File
    • 2.4 The Antenna Rule-File
    • 2.5 Device Generators
  • 3 Standard Cell Place and Route Design Flow
    • 3.1 Importing a Verilog Netlist
    • 3.2 Creating A Cell
    • 3.3 Setting the Powerstyles
    • 3.4 Autofloorplan
    • 3.5 Autoplace Ports
    • 3.6 Creating a core block for AutoCells
    • 3.7 Running AutoCells for standard cell blocks
    • 3.8 Autoplace Corner Cells
    • 3.9 Autoroute
    • 3.10 Compact
    • 3.11 Insert Peri Spacer Cells
  • 4 Schematic Driven Layout Design Flow
  • 5 Layout Verification
    • 5.1 Text Concept
    • 5.2 ICrules - Interactive DRC
    • 5.3 Mask Layer Generation
    • 5.4 Antenna Rule Check
    • 5.5 ICtrace(M) - Interactive LVS
    • 5.6 Calibre DRC
    • 5.7 Calibre LVS
    • 5.8 Calibre Utilities
    • 5.9 Read and Write GDSII
  • 6 Parasitic Extraction and Backannotation
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