Assura Known Problems
DRC
- Make sure that the correct technology file is attached to your library.
- Check that Rules Library and Rules file are set correctly in the DRC form.
LVS
- Make sure that the correct techfile is attached to your library.
- Check that Technology and Rules file are set correctly in the form.
- Does your LVS window really contain the schematic and layout design source you want to check?
- Make sure that the LVS mode is set correctly (Rule set: Full or Macro).
- Make sure you set the UNIX environment variable: setenv CDS_Netlisting_Mode Analog
- Be aware that Cadence Macro LVS does not work correctly with the Assura version this HIT-Kit is qualified for!
- With Macro LVS you might get 'METX pin outside metx' messages in the ErrorLayer Window that can be ignored as long as they concern abstract_mlvs views of austriamicrosystems standard cells.
- Further Macro LVS might report extraction problems for the power supply pads that also can be ignored as long as they concern only abstract_mlvs views of austriamicrosystems power pads.
RCX
- Make sure that the correct technology file is attached to your library.
- Check that the Technology is set correctly in the Extractor form.
- Make sure the correct "Ref Node" is set.