Design Flows
Custom Cell Layout Design Flow
- Manually perform the cell layout using Virtuoso(XL)
- Perform a design rule check
- Run a transistor level LVS
- After successful LVS, use Assura RCX to get an analog-extracted view.
- Resimulate the design using the extracted view.
- Automatically generate the generated layers
and metal fill structures if required.
The scripts to do this are located in the directory $AMS_DIR/assura/<technology>
- Perform a final DRC without selecting any switches.
Standard Cell Layout Design Flow
- Perform layout with Silicon Ensemble / Cell Ensemble or place Standard
Cells with Virtuoso(XL).
- Import data from Silicon Ensemble into Cadence layout view
(see
Silicon Ensemble User's Guide:
Data to and from Silicon Ensemble)
If using Cell Ensemble from a previous Cadence version change to Virtuoso(XL)
- Replace all views with "abstract_mlvs" view
- SE: Within Cadence/Virtuoso replace all views using: Edit -> Search -> Replace
- Perform a design rule check with no switches set.
- Run the Macro LVS (Rule Set: Macro)
- After layout with Silicon Ensemble or Cell Ensemble extract the parasitics
for resimulation.
- After successful Macro LVS and if the layout view of standard cells is
available continue with the following steps:
- Replace the "abstract_mlvs" view with the "layout" view
- Run a full DRC
- Run the final transistor level LVS.
