Parasitic Layout Extraction
After you've got a clean LVS without using the resimulate_extracted switch (to guarantee that also substrate shorts are found correctly) another LVS has to be performed now using the resimulate_extracted switch to get the correct connectivity for parasitic layout extraction (PEX).
Assura -> Run LVS...
Switch Names: resimulate_extracted
With also this LVS run clean you can start PEX to extract devices plus interconnect parasitics for accurate postlayout
simulation.
Assura RCX extraction is invoked from a Virtuoso or VirtuosoXL window through the
menu:
Assura -> Run RCX...
To perform a transistor level extraction, the following options should be set:
Setup subwindow:
- Check that the Technology
is correctly specified.
- Output should be set to Extracted View if you
want to do a post layout simulation
using the Analog Design Environment.
- Make sure that Extract MOS Diffusion Res is selected.
Extraction subwindow:
- Always specify the Ref Node correctly!
- Set Cap Extraction Mode to Coupled.
- Extraction Mode may be set to your demands.
Extraction of parasitic inductors
is currently not supported.