Assura LVS - Layout versus Schematic Check

 

Assura is basically doing an hierarchical LVS. Two modes can be selected: either Full LVS going down to transistor level or Macro LVS handling defined standard cells as black boxes.

Be aware that Cadence Macro LVS does not work correctly with the Assura version this HIT-Kit is qualified for!

Assura LVS is invoked from a Virtuoso or VirtuosoXL window through the menu:

Assura -> Run LVS...

 

Full LVS:


Make sure that the correct Technology and Extract Rules are set and that Rule Set -> Full is selected.
Do NOT use the resimulate_extracted switch because in that case substrate shorts might not be found correctly!
Other parameters depend on your demands.

Using IP-Blocks:

For IP-Blocks where only an abstract view but no full layout information is available a so called black-box-cell definition is required.
Make sure the following is available for the IP-Block:

  • An abstract view with all pins. The pin shapes have to be on 'METX drawing' layers with a pin name label on layer 'PIN metx' placed over the pin shapes. Further it's recommended to have the pin information also on 'METX pin' shapes with the same size as the 'METX drawing' shapes.
  • A symbol view with all pins
  • A dummy schematic view with all pins and at least one device like a presistor in it. Without a schematic the netlister would fail. It's however not important what's in the schematic except the pins. As soon as the IP-Block is defined as black-box-cell LVS considers the pins but doesn't look into the cell anymore.

In the LVS dialog box:

  • Click on Modify avParameters
  • Select ?blackBoxCell
  • Select Use in Run
  • Enter the name(s) of the IP-Block(s) in the Cells field

Now LVS can be started and the specified IP-Block(s) will be treated as black-box-cell(s).
For more information on the usage of black-box-cells please refer to the Cadence manuals.

 

Macro LVS:

Running a Macro LVS some more things have to be considered.
First of all make sure the correct Technology and Extract Rules are set and that Rule Set -> Macro is selected. If your design includes IO-Cells you need the changeLabel function to set the powerring names correct for macro LVS:

 => Modify changeLabel Function

       vdd3r1! => vdd3r!
       vdd3r2! => vdd3r!
       gnd3o!  => gnd!
       gnd3r!  => gnd!

This is not required if you're using only core cells.

Further you need to place a DFII pin with the top metal layer with purpose "pin" on all pads (e.g. "MET4" "pin" in technology C35B4). On the DFII pin always place a label with layer "PIN"  and purpose "pad" to allow Assura to recognize the top level pins correctly.

Be aware that Cadence does not officially support Macro LVS for this Assura version so it can't be guaranteed that it will work in every case! 
There's a known Cadence bug that inherited connections within hierarchical cells do not work correctly with macro LVS!

You might get 'METX pin outside metx' messages in the ErrorLayer Window that can be ignored as long as they concern abstract_mlvs views of austriamicrosystems standard cells.
Further Macro LVS might report extraction problems for the power supply pads that also can be ignored as long as they concern only abstract_mlvs views of austriamicrosystems power pads.

 

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