Assura Design Rule Check
The rule file for DRC enables online checking during the design phase and performing final verification before tape-out. For final verification you should note that the Standard Family Cells do not conform to the design rules and these cells should be excluded from the design rule check. A simple method is to generate a level of hierarchy on top of the final layout which instantiates all cells from SFCLIB.
Assura DRC is invoked from a Virtuoso or VirtuosoXL window through the menu:
Assura -> Run DRC...
The following form will pop up:
Check, that the "Rules File" and "Technology" are correctly specified (must correspond to your design technology!).
If you want to set switches, then you have to push the "Set Switches" button, which will bring up another form where you can select between various switches:
Before submitting any data for fabrication, a DRC check must be run without
any switches. During the design phase the following switches may be used:
(The table shows, which switches are available in the various technologies)
switch | C35B3 | C35B4 | S35D3 | S35D4 | H35B3 | H35B4 | BYQ | CXQ | CXZ |
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X |
X |
X |
X |
X | X |
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| X |
csxswitch
Allows to switch off some checks and 'relax' some checks for technology C35/B35
that would cause DRC errors in 'CSX' layouts which have been transformed to
technology C35/B35.
device_debug
Reports all recognized devices in the DRC results database.
gds2input
Has to be used if your input for Assura is a GDSII database. Therefore set:
Layout Design Source => Stream
Rule Set ==> gdsII
grid
Allows to check for offgrid structures. It is recommended to use the grid of 0.1µm
or 0.05µm but is not absolutely necessary. In the mask shop the layout snaps to a
grid of 0.01µm. Normally grid violations are uncritical but these could cause
systematic mismatch when offgrid geometries are used for high precision analog elements.
no_antenna
Allows to switch off antenna checks.
no_coverage
This switch can be used to disable the checks for metal and poly coverage when
performing DRC.
no_elements
Disables element specific checks.
no_erc
ERC is switched off (floating POLY1, floating POLY2, PSUB without TAP ...)
no_generated_layers
Disables the checks for generated layers like FIMP, NLDD and NLDD50 when
performing DRC.
no_holes
Disables MetX-hole checks.
no_info
Disables all checks that are only for informational purpose (not included in the
Design Rule Document)
no_recommendation
Disables all checks that consider recommendations.
nleak_pleak_checks
Enables a check to find possible parasitic transistors in high voltage
designs.
Viewing DRC Errors
After performing a DRC, the reported DRC errors are shown in the Error Layer Window (menu: Assura -> Open ELW):
Correcting DRC Errors
the scripts described in the following section can be used on demand except
the script 'laygen' that has to be used to generate required layers like FIMP,
NLDD and NLDD50.
Fill Notches:
The script notchfill will generate metal structures to fill the metal notches (for example caused by Silicon Ensemble). After finishing your P&R you have to:
- Copy directory $AMS_DIR/assura/technology/notchfill to your working directory
- Edit File ‘RSF’ and enter the name of your GDSII file got from SE, the name of the top cell and the name for the GDSII result file.
- Start Assura in the local ‘notchfill’ directory using: assura RSF
- Stream in the GDSII result file into the Cadence DFII Environment
Fill Top-Metal:
The script fillmettop will generate metal structures on your top level metal layer to avoid maximum top metal spacing errors.
- Copy directory $AMS_DIR/assura/technology/fillmettop to your working directory
- Stream out your Cadence layout to GDSII.
- Edit File ‘RSF’ and enter the name of your GDSII file, the name of the top cell and the name for the GDSII result file.
- Start Assura in the local ‘fillmettop’ directory using: assura RSF
- Note that when you import the resulting GDSII file the Cadence layout will have the same name as your original layout. In order not to overwrite your original layout import the layout with the generated layers in a separate Cadence library!
- Then you can copy it with a different name to your original design library and insert it as a layout cell in your top-level layout.
Fill Pattern:
The script fillpattern will generate metal structures on all metal layers except top metal to reach the required metal densities.
- Copy directory $AMS_DIR/assura/technology/fillpattern to your working directory
- Stream out your Cadence layout to GDSII.
- Edit File ‘RSF’ and enter the name of your GDSII file got from SE, the name of the top cell and the name for the GDSII result file.
- Start Assura in the local ‘fillpattern’ directory using: assura RSF
- Note that when you import the resulting GDSII file the Cadence layout will have the same name as your original layout. In order not to overwrite your original layout import the layout with the generated layers in a separate Cadence library!
- Then you can copy it with a different name to your original design library and insert it as a layout cell in your top-level layout.
Generate Layers:
After finishing your layout (DRC error free with switch ‘no_generated_layers’ and LVS clean) you can have the layers FIMP, NLDD and NLDD50 for technology C35B3/B4 generated automatically using the script laygen.
- Copy directory $AMS_DIR/assura/technology/laygen to your working directory.
- Stream out your Cadence layout to GDSII.
- Edit File ‘RSF_technology_laygen’ and enter the name of your GDSII file, the name of the top cell and the name for the GDSII result file that will include the generated layers.
- Start assura in the local ‘laygen’ directory using: assura RSF_technology_laygen.
- Note that when you import the resulting GDSII file the Cadence layout will have the same name as your original layout. In order not to overwrite your original layout import the layout with the generated layers in a separate Cadence library!
- Then you can copy it with a different name to your original design library and insert it as a layout cell in your top-level layout.
- Finally you have to perform a DRC without switching off any checks.