HIT-Kit - Cadence based design flow
Design Flow
- Framework: Design Framework II (AnalogArtist)
- Schematic Design Creation: Composer Circuit Design Entry
- Register Transfer Level Creation: HDL Designer [Mentor]
- Behavioral Modelling: VHDL * Verilog * Verilog A * SpectreHDL * Verilog AMS * VHDL AMS
- Logic Synthesis & Optimization: Design Compiler [Synopsys] * BuildGates /PKS [Cadence]
- ATPG: Tetramax [Synopsys] * Fastscan/Flextest [Mentor]
- Simulation
Behavioral: Verilog-XL * NCSim * Spectre HDL * ModelSim [Mentor]
Digital: Verilog-XL * NCSim * ModelSim [Mentor]
Analog: Spectre * UltraSim * HSIM [Synopsys] * Eldo [Mentor] * hspice [Synopsys] RF: Spectre RF * ADS [Agilent]
Mixed Signal: SpectreVerilog * AMS Designer
- Place & Route: First Encounter * Silicon Ensemble * IC-Craftsman
- Layout : Virtuoso Layout Editor * ROD Pcells (available in Mixed-Signal HIT-Kit only)
- Verification: Assura * Calibre [Mentor] * Diva
Trademarks: Advanced Design System, RFDE and Dynamic Link are trademarks of Agilent Technologies, Inc., Cadence, the Cadence logo and First Encounter are registered trademarks, and Encounter, Assura, Cadence NCSim and BuildGates are trademarks of Cadence Design Systems, Inc., ModelSim, Artist Link and Calibre are trademarks of Mentor Graphics Corporation. All other trademarks are the property of their respective owners. Copyright (c) 2005 austriamicrosystems AG