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Please note: Universities, Academic and Educational Institutions are kindly asked to order the HIT-Kit directly from CMP, EUROPRACTICE, Fraunhofer IIS or MOSIS, our longtime partners taking care of our MPW and low volume customers worldwide.
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General Information
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INFO: HIT-Kit data is provided on DVD-ROM for Sun/Solaris 7/8/9 and Red Hat EL 3.0
0.35µm 0.8µm C35 S35 H35 CXQ CXZ BYQ HIT-Kit v3.72
Cadence IC5.1.41usr5 (3)DIGITAL
MIXED-SIGNAL(5) HIT-Kit v3.70
Cadence IC5.1.41 (3)DIGITAL
MIXED-SIGNAL(5) HIT-Kit v3.71
Mentor IC Flow 2005.1 (4)DIGITAL
MIXED-SIGNAL(5) HIT-Kit v3.70
Mentor IC Flow 2005.1 (4)DIGITAL
MIXED-SIGNAL(5) HIT-Kit v3.40
Mentor IC Flow 2001.3 (4)DIGITAL MIXED-SIGNAL(5)
(1) The required Confidentiality Agreement (CA/NDA) number (6 digits) can be found on the bottom left corner on the last page of your Confidentiality Agreement (Geheimhaltungsvertrag).
If there is no Confidentiality Agreement in place yet with austriamicrosystems, please contact your local Sales Office.(2) Please note that there must be also a HIT-Kit License Agreement in place before the HIT-Kit DVD-ROM may be delivered (N.B. This applies also for the download of the ADS Agilent HIT-Kit). (3) CADENCE HIT-Kits include also Silicon Ensemble data, First Encounter data (0.35µm), simulation parameters, verification rule sets, synthesis and inductor libraries. (4) MENTOR HIT-Kits include also IC Station data, simulation parameters, verification rule sets and synthesis libraries. (5) MIXED-SIGNAL HIT-Kits include the Digital HIT-Kit plus a complete set of analog libraries, pcells, 3-bus libraries, package library, RF pads for mixed-mode designs and are therefore subject to license fee!
Download Area
Following data can be downloaded by registered customers directly from http://asic.austriamicrosystems.com/cgi-sbin/download_area_index.cgi:
- GDSII layout of Standard Family Cells, Analog Periphery Cells, Powercut Cells, and Primitive devices.
- Circuit Simulation Parameters for Eldo, EldoS, SpectreS, SpectreDirect, HSpiceS, Smash, Saber, Pspice, ADSsim, and SmartSpice.
- Digital Simulation and Synthesis Libraries for BuildGates, Liberty, Synopsys, TLF, Vital, and Verilog.
- Memory Simulation Models (SPRAM, DPRAM, DROM)
- Package Lead Frames (PDF format)
- Agilent ADS HIT-Kits
- Controlled Design Documents (Design Rules and Process Parameter documents)
No Implied Offer
The usage of austriamicrosystems AG design kits and/or libraries or the participation on Multi Product Wafer runs (MPW) shall not be regarded as an implied offer by austriamicrosystems AG to subsequently manufacture such integrated circuits. Each integrated circuit, which is planned for production requires an official quotation by austriamicrosystems AG.
Please fax this form to Design Support Group / Austria
Fax: +43 3136 500-5755
Thank you !
Trademarks:
Synopsys is a registered trademark and Liberty is a trademark of Synopsys, Inc., Advanced Design System, RFDE and Dynamic Link are trademarks of Agilent Technologies, Inc., Cadence, the Cadence logo and First Encounter are registered trademarks, and Encounter, Assura, Cadence NCSim, Verilog and BuildGates are trademarks of Cadence Design Systems, Inc., ICstudio, DA-IC, IC-Station, AutoCells, ADMS, Eldo, ICnet, DMGR-IC, DVE-IC, ModelSim, Artist Link and Calibre are trademarks of Mentor Graphics Corporation, Sun and Solaris are registered trademarks of Sun Microsystems, Inc., HP-UX is a registered trademark of Hewlett-Packard Company. All other trademarks are the property of their respective owners.
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