The Concept of Power-Cut Cells

 

These cells are used for the separation of different power domains, but still maintaining an ESD discharge path between them. Even if the separation of the substrate is limited by the substrate resistance itself, some applications however need power-cut cells to reduce the noise coupling between analog and digital circuitry. Moreover it is very important to have a closed periphery power ring in order to reduce the overall resistance on the power lines for ESD, thus at least 2 PWRCUT cells need to be placed. Power-cut cells are available for pad-limited and core-limited versions of periphery cells. For more recommendations in order to achieve best ESD performance, please see chapter Selection Criteria.

Types of Power-Cut Cells

There are different types of Power-cuts in our library. They are used as Glue-Cells and can be found in IOLIB_xx, category GLUE_CELLS. Depending on the substrate connection there are 2/4 choices of Power-Cut cells, which differ in the protection elements placed in the gap between the power and ground buses (in the following sorted by ESD Performance):

  • xx_DX:
    		• VSS (2B): antiparallel diodes VDD: no diodes        
  • xx_DD:
    		• VSS (2B): antiparallel diodes VDD: antiparallel diodes, use for double bond of VDDs only!                
  • xx_DXS:
    		• VSS (3B): antiparallel diodes VDD: no diodes SUB: shorted
  • xx_DXD:
    		• VSS (3B): antiparallel diodes VDD: no diodes SUB: antiparallel diodes
  • xx_DDS:
    		• VSS (3B): antiparallel diodes VDD: antiparallel diodes SUB: shorted, use for double bond of VDDs only!
  • xx_DDD:
    		• VSS (3B): antiparallel diodes VDD: antiparallel diodes SUB: antiparallel diodes, use for double bond of VDDs only!

    In the 2B (2-Bus power system) versions VSS and SUB are tied together. In the 3B (3-Bus power system) versions the SUB power routing is separate from VSS. In most applications the noisy VSS must be separated between DIG and ANA, so the SUB can be connected together. Antiparallel diodes add an additional voltage drop of ~1V during an ESD strike, in addition to the metal bus wiring. The overall metal bus resistance of VSS/SUB and the VDD net must be less than 3 Ohms for 2kV HBM level (2V drop for 2 PWRCUTs is 2V / 1.3A = 1.5 Ohms!).

     

    Naming of Power-Cut Cells

    The names of the Power-Cut cells follow the syntax:

      PWRCUT_<Design Type>_<Pad-Version>_<Device between VSS>_<Device_between_VDD>_<Device_between_SUB>
  • Design Type
    		• ANA or DIG
  • Pad-Version
    		• P for padlimited or C for corelimited
  • Device between VSS
    		• DIODE , Short recommended
  • Device between VDD
    		• no DIODE or DIODE
  • Device between SUB
    		• Short or DIODE

    For example: PWRCUT_ANA_P_DXS means

  • ANA
    		• placing between two Analog-Supply
  • P
    		• padlimited Version
  • D
    		• antiparallel Diodes between VSS
  • X
    		• no Diodes between VDD
  • S
    		• Short between SUB

    Following cells exist:

    Cell Name Purpose
    PWRCUT_DIG_P_DD Power-Cut for padlimited digital Peri-Cells
    PWRCUT_DIG_C_DD Power-Cut for corelimited digital Peri-Cells
    PWRCUT_ANA_P_DD Power-Cut for padlimited analog Peri-Cells
    PWRCUT_ANA_C_DD Power-Cut for corelimited analog Peri-Cells
    PWRCUT_DIG_P_DX Power-Cut for padlimited digital Peri-Cells
    PWRCUT_DIG_C_DX Power-Cut for corelimited digital Peri-Cells
    PWRCUT_ANA_P_DX Power-Cut for padlimited analog Peri-Cells
    PWRCUT_ANA_C_DX Power-Cut for corelimited analog Peri-Cells
    PWRCUT_DIG_P_DXS Power-Cut for padlimited digital Peri-Cells
    PWRCUT_DIG_C_DXS Power-Cut for corelimited digital Peri-Cells
    PWRCUT_ANA_P_DXS Power-Cut for padlimited analog Peri-Cells
    PWRCUT_DIG_P_DXD Power-Cut for padlimited digital Peri-Cells
    PWRCUT_DIG_C_DXD Power-Cut for corelimited digital Peri-Cells
    PWRCUT_ANA_P_DXD Power-Cut for padlimited analog Peri-Cells

    Existence of Cells

    1.For the following one or two buses all combinations of DIODE or no-Diode/Short are available.
    2.When there are 5 buses (digital padlimited cells) the last two buses have the same combinations as the previous two buses.

    When this is applied to the different cell groups following powercut cells come into existence: 

                                    Protection between
Cell Group/Name                 VSS-Substrate   1.VDD   2.VSS   3.VSS   2.VDD 

Digital Padlimited:
PWRCUT_DIG_P_DDD                DIODE           DIODE   DIODE   DIODE   DIODE
PWRCUT_DIG_P_DXD                DIODE            --     DIODE   DIODE    --
PWRCUT_DIG_P_DDS                Short           DIODE   DIODE   DIODE   DIODE
PWRCUT_DIG_P_DXS                Short            --     DIODE   DIDOE    --   
   
Digital Corelimited:
PWRCUT_DIG_C_DDD                DIODE           DIODE   DIODE     *)      *)
PWRCUT_DIG_C_DXD                DIODE            --     DIODE     *)      *)
PWRCUT_DIG_C_DDS                Short           DIODE   DIODE     *)      *)
PWRCUT_DIG_C_DXS                Short            --     DIODE     *)      *)

Analog Padlimited:
PWRCUT_ANA_P_DDD                DIODE           DIODE   DIODE     *)      *)
PWRCUT_ANA_P_DXD                DIODE            --     DIODE     *)      *)
PWRCUT_ANA_P_DDS                Short           DIODE   DIODE     *)      *)
PWRCUT_ANA_P_DXS                Short            --     DIODE     *)      *)


PWRCUT_ANA_C_DD                 DIODE           DIODE    *)       *)      *)
PWRCUT_ANA_C_DX                 DIODE            --      *)       *)      *)

*) This bus does not exist in this cell group

     

    Selection Criteria

    (See also LV ESD Design Rule Document No. ENG-236)
    Preferred are the DX and DXS versions since they are the best trade off between ESD and noise decoupling. From an ESD point of view the DXS with (manually) shorted VSS-Bus is the best choice as the overall bus resistance is kept low. In any case each power domain must have its own ESD clamp, and during power up there is no influence from one power domain to the other.

    For higher ESD rating than 2kV HBM either a low ohmic GND Bus is provided or interface cells and PWRCUTs between 2 power domains are required for an ESD safe solution. Only for the double bond option of 2 VDDs the "xDx" type of PWRCUT can be used (In case of two different VDDs the antiparallel diodes can cause latchup during the power up sequence because of a forward current from one VDD to the other).

    As long as the pins are not bonded the antiparallel diodes are used for wafer level ESD protection.

    To interface between two different types of power bus systems (e.g. between digital pad-limited and analog core-limited) choose the power cut cell with more power buses.

    Note: All power buses must be connected, e.g. the two VDD buses on the digital side will then be connected via protection elements to only one VDD bus on the analog side.

    ATTENTION: Don't use these cells for voltage differences greater than 7 Volt above substrate (e.g. H35 high voltage process), i.e. be careful with mixing floating and non-floating logic!

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