Notes

The floating digital cells are characterized for 3.3 Volts with nonlinear delays dependent on input slope and output load, which gives timing accuracy similar to a circuit simulator.

The floating cells operate at 3.3V (VDD-VSS) and can float in respect to the substrate fom 0V to 50V.

Power Calculation

Power consumption figures for all cells are calculated under the following conditions:

Input slope = 1ns

Output load = 20 fF * drive strength for the core cells.

Output load = 2.5 pF * drive strength for the periphery cells.

The applied testpattern for power calculation covers all possible input combinations for combinatorial cells and therefore provides an averaging of power for all possible input patterns. Sequential cells are related to their clock-input signal. The values are given in µW and are related to a 1MHz toggling frequency. For other frequencies the given number must be linearly scaled.

When I/O cells with Pull-up or Pull-down function (e.g. BBCUxP and BBCDxP) are used in input mode with a high-impedance signal on the PAD pin they will always generate a logical 1 (pull-up) or logical 0 (pull-down) at the internal Y pin. This situation is however modelled in our Verilog and VHDL simulation with an X state at the output, this is shown in the truth-tables provided.

For all cells the following output transitions are defined as "Rise" or "Fall". The transitions to/from a high-impedance "Z" state are only used for tri-state cells (e.g. BTx, ITx, BTxP, BUDDxP and BUDUxP).

Under certain conditions, delay calculations may result in negative delay values.

These ‘negative delays’ are mainly caused by the difference between timing acquisition and the physical cell threshold as shown in the drawing below.

Note: Negative delays are set to "0" by some simulation tools.

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