h35 Cells

 

h35 HV Cells by Name

Notes

Half Adders   Area  
[µm²]		 Power
[µW/MHz]
ADD21_HVHalf-Adder (1x)146 0.91 
ADD22_HVHalf-Adder (2x)146 1.75 
Full Adders   Area  
[µm²]		 Power
[µW/MHz]
ADD31_HVFull-Adder (1x)273 1.13 
ADD32_HVFull-Adder (2x)273 2.10 
AND-OR-INVERT Gates   Area  
[µm²]		 Power
[µW/MHz]
AOI210_HV2-Input AND into 2-Input NOR (0.5x)73 0.26 
AOI211_HV2-Input AND into 2-Input NOR (1x)73 0.49 
AOI212_HV2-Input AND into 2-Input NOR (2x)91 0.90 
AOI2110_HV2-Input AND into 3-Input NOR (0.5x)91 0.35 
AOI2111_HV2-Input AND into 3-Input NOR (1x)91 0.66 
AOI2112_HV2-Input AND into 3-Input NOR (2x)127 1.19 
AOI220_HV2x2-Input AND into 2-Input NOR (0.5x)91 0.33 
AOI221_HV2x2-Input AND into 2-Input NOR (1x)91 0.60 
AOI222_HV2x2-Input AND into 2-Input NOR (2x)109 1.10 
AOI310_HV3-Input AND into 2-Input NOR (0.5x)91 0.32 
AOI311_HV3-Input AND into 2-Input NOR (1x)91 0.62 
AOI312_HV3-Input AND into 2-Input NOR (2x)109 1.18 
Tri-State Buffers   Area  
[µm²]		 Power
[µW/MHz]
BUFE2_HVTri-State Buffer with active high enable (2x)146 0.84 
BUFE4_HVTri-State Buffer with active high enable (4x)164 1.59 
BUFE6_HVTri-State Buffer with active high enable (6x)182 2.28 
BUFE8_HVTri-State Buffer with active high enable (8x)255 3.14 
BUFE10_HVTri-State Buffer with active high enable (10x)273 3.83 
BUFE12_HVTri-State Buffer with active high enable (12x)328 4.54 
BUFE15_HVTri-State Buffer with active high enable (15x)364 5.67 
Tri-State Buffers   Area  
[µm²]		 Power
[µW/MHz]
BUFT2_HVTri-State Buffer with active low enable (2x)146 0.83 
BUFT4_HVTri-State Buffer with active low enable (4x)164 1.59 
BUFT6_HVTri-State Buffer with active low enable (6x)182 2.29 
BUFT8_HVTri-State Buffer with active low enable (8x)255 3.13 
BUFT10_HVTri-State Buffer with active low enable (10x)273 3.84 
BUFT12_HVTri-State Buffer with active low enable (12x)328 4.54 
BUFT15_HVTri-State Buffer with active low enable (15x)364 5.67 
Buffers   Area  
[µm²]		 Power
[µW/MHz]
BUF2_HVBuffer (2x)55 0.84 
BUF4_HVBuffer (4x)73 1.60 
BUF6_HVBuffer (6x)73 2.36 
BUF8_HVBuffer (8x)91 3.22 
BUF12_HVBuffer (12x)109 4.67 
BUF15_HVBuffer (15x)146 5.95 
Bus Holder   Area  
[µm²]		 Power
[µW/MHz]
BUSHD_HVBusholder55 0.00 
Clock Buffers   Area  
[µm²]		 Power
[µW/MHz]
CLKBU2_HVSymmetrical Buffer for clock tree synthesis (2x)55 0.72 
CLKBU4_HVSymmetrical Buffer for clock tree synthesis (4x)73 1.37 
CLKBU6_HVSymmetrical Buffer for clock tree synthesis (6x)73 2.00 
CLKBU8_HVSymmetrical Buffer for clock tree synthesis (8x)91 2.93 
CLKBU12_HVSymmetrical Buffer for clock tree synthesis (12x)109 4.20 
CLKBU15_HVSymmetrical Buffer for clock tree synthesis (15x)146 5.24 
Clock Gating Cells   Area  
[µm²]		 Power
[µW/MHz]
DLSG1_HVClock gating cell 219  0.8 
Clock Inverters   Area  
[µm²]		 Power
[µW/MHz]
CLKIN0_HVSymmetrical Inverter for clock tree synthesis (0.5x)36 0.17 
CLKIN1_HVSymmetrical Inverter for clock tree synthesis (1x)36 0.32 
CLKIN2_HVSymmetrical Inverter for clock tree synthesis (2x)36 0.63 
CLKIN3_HVSymmetrical Inverter for clock tree synthesis (3x)36 0.94 
CLKIN4_HVSymmetrical Inverter for clock tree synthesis (4x)55 1.21 
CLKIN6_HVSymmetrical Inverter for clock tree synthesis (6x)55 1.79 
CLKIN8_HVSymmetrical Inverter for clock tree synthesis (8x)73 2.46 
CLKIN10_HVSymmetrical Inverter for clock tree synthesis (10x)91 3.02 
CLKIN12_HVSymmetrical Inverter for clock tree synthesis (12x)91 3.61 
CLKIN15_HVSymmetrical Inverter for clock tree synthesis (15x)109 4.54 
D-Type Flip-Flops   Area  
[µm²]		 Power
[µW/MHz]
DF1_HVD-Type Flip Flop (1x)273 1.14 
DF3_HVD-Type Flip Flop (3x)273 1.80 
DFC1_HVD-Type Flip Flop with active low clear (1x)310 1.22 
DFC3_HVD-Type Flip Flop with active low clear (3x)310 1.88 
DFCP1_HVD-Type Flip Flop with active low clear and preset (1x)328 1.31 
DFCP3_HVD-Type Flip Flop with active low clear and preset (3x)328 1.97 
DFP1_HVD-Type Flip Flop with active low preset (1x)310 1.21 
DFP3_HVD-Type Flip Flop with active low preset (3x)310 1.89 
DFS1_HVScan D-Type Flip Flop (1x)364 1.27 
DFS3_HVScan D-Type Flip Flop (3x)382 1.92 
DFSC1_HVScan D-Type Flip Flop with active low clear (1x)382 1.36 
DFSC3_HVScan D-Type Flip Flop with active low clear (3x)401 2.02 
DFSCP1_HVScan D-Type Flip Flop with active low clear and preset (1x)401 1.46 
DFSCP3_HVScan D-Type Flip Flop with active low clear and preset (3x)419 2.11 
DFSP1_HVScan D-Type Flip Flop with active low preset (1x)382 1.36 
DFSP3_HVScan D-Type Flip Flop with active low preset (3x)401 2.02 
DFE1_HVD-Type Flip Flop with active high enable (1x)328 1.33 
DFE3_HVD-Type Flip Flop with active high enable (3x)346 1.98 
DFEC1_HVD-Type Flip Flop with active high enable and active low clear (1x)346 1.41 
DFEC3_HVD-Type Flip Flop with active high enable and active low clear (3x)364 2.06 
DFECP1_HVD-Type Flip Flop with active high enable, active low clear and preset (1x)382 1.49 
DFECP3_HVD-Type Flip Flop with active high enable, active low clear and preset (3x)401 2.15 
DFEP1_HVD-Type Flip Flop with active high enable and active low preset (1x)346 1.40 
DFEP3_HVD-Type Flip Flop with active high enable and active low preset (3x)364 2.05 
DFSE1_HVScan D-Type Flip Flop with active high enable (1x)419 1.42 
DFSE3_HVScan D-Type Flip Flop with active high enable (3x)437 2.08 
DFSEC1_HVScan D-Type Flip Flop with active high enable and active low clear (1x)437 1.50 
DFSEC3_HVScan D-Type Flip Flop with active high enable and active low clear (3x)455 2.16 
DFSECP1_HVScan D-Type Flip Flop with active high enable, active low clear and preset (1x)455 1.59 
DFSECP3_HVScan D-Type Flip Flop with active high enable, active low clear and preset (3x)473 2.25 
DFSEP1_HVScan D-Type Flip Flop with active high enable and active low preset (1x)437 1.50 
DFSEP3_HVScan D-Type Flip Flop with active high enable and active low preset (3x)455 2.16 
Data Latches   Area  
[µm²]		 Power
[µW/MHz]
DL1_HVData Latch (1x)200 1.22 
DL3_HVData Latch (3x)200 2.55 
DLC1_HVData Latch with active low clear (1x)219 1.36 
DLC3_HVData Latch with active low clear (3x)219 2.68 
DLCP1_HVData Latch with active low clear and preset (1x)237 1.45 
DLCP3_HVData Latch with active low clear and preset (3x)237 2.78 
DLP1_HVData Latch with active low preset (1x)200 1.30 
DLP3_HVData Latch with active low preset (3x)200 2.64 
DLQ1_HVData Latch with Q-output only (1x)182 0.33 
DLQ3_HVData Latch with Q-output only (3x)182 0.39 
DLCQ1_HVData Latch with Q-output only and active low clear (1x)182 1.12 
DLCQ3_HVData Latch with Q-output only and active low clear (3x)182 1.95 
DLCPQ1_HVData Latch with Q-output only, active low clear and preset (1x)200 0.53 
DLCPQ3_HVData Latch with Q-output only, active low clear and preset (3x)200 1.17 
DLPQ1_HVData Latch with Q-output only and active low preset (1x)182 0.94 
DLPQ3_HVData Latch with Q-output only and active low preset (3x)182 1.59 
Delay Buffers   Area  
[µm²]		 Power
[µW/MHz]
DLY12_HVSingle Delay (2x)164 1.74 
DLY22_HVDouble Delay (2x)219 2.65 
DLY32_HVTriple Delay (2x)310 3.45 
DLY42_HVQuadr. Delay (2x)401 4.41 
Inverting Majority   Area  
[µm²]		 Power
[µW/MHz]
IMAJ30_HVInverting Majority ~(AB+AC+BC), (0.5x)109 0.27 
IMAJ31_HVInverting Majority ~(AB+AC+BC), (1x)109 0.53 
Inverting Multiplexers   Area  
[µm²]		 Power
[µW/MHz]
IMUX20_HVInverting 2:1 Multiplexer (0.5x)91 0.25 
IMUX21_HVInverting 2:1 Multiplexer (1x)91 0.48 
IMUX22_HVInverting 2:1 Multiplexer (2x)146 0.93 
IMUX23_HVInverting 2:1 Multiplexer (3x)146 1.15 
IMUX24_HVInverting 2:1 Multiplexer (4x)182 1.71 
IMUX30_HVInverting 3:1 Multiplexer (0.5x)182 0.46 
IMUX31_HVInverting 3:1 Multiplexer (1x)219 0.87 
IMUX32_HVInverting 3:1 Multiplexer (2x)237 1.52 
IMUX33_HVInverting 3:1 Multiplexer (3x)364 2.41 
IMUX40_HVInverting 4:1 Multiplexer (0.5x)219 0.44 
IMUX41_HVInverting 4:1 Multiplexer (1x)255 0.86 
IMUX42_HVInverting 4:1 Multiplexer (2x)364 1.56 
Inverters   Area  
[µm²]		 Power
[µW/MHz]
INV0_HVInverter (0.5x)36 0.17 
INV1_HVInverter (1x)36 0.34 
INV2_HVInverter (2x)36 0.65 
INV3_HVInverter (3x)36 0.96 
INV4_HVInverter (4x)55 1.24 
INV6_HVInverter (6x)55 1.84 
INV8_HVInverter (8x)73 2.52 
INV10_HVInverter (10x)91 3.09 
INV12_HVInverter (12x)91 3.71 
INV15_HVInverter (15x)109 4.67 
JK Flip-Flops   Area  
[µm²]		 Power
[µW/MHz]
JK1_HVJK Flip-Flop (1x)346 1.29 
JK3_HVJK Flip-Flop (3x)346 1.96 
JKC1_HVJK Flip-Flop with active low clear (1x)364 1.38 
JKC3_HVJK Flip-Flop with active low clear (3x)364 2.04 
JKCP1_HVJK Flip-Flop with active low clear and preset (1x)382 1.46 
JKCP3_HVJK Flip-Flop with active low clear and preset (3x)382 2.12 
JKP1_HVJK Flip-Flop with active low preset (1x)364 1.38 
JKP3_HVJK Flip-Flop with active low preset (3x)364 2.04 
JKS1_HVScan JK Flip-Flop (1x)437 1.45 
JKS3_HVScan JK Flip-Flop (3x)437 2.10 
JKSC1_HVScan JK Flip-Flop with active low clear (1x)455 1.53 
JKSC3_HVScan JK Flip-Flop with active low clear (3x)455 2.19 
JKSCP1_HVScan JK Flip-Flop with active low clear and preset (1x)473 1.61 
JKSCP3_HVScan JK Flip-Flop with active low clear and preset (3x)473 2.27 
JKSP1_HVScan JK Flip-Flop with active low preset (1x)455 1.53 
JKSP3_HVScan JK Flip-Flop with active low preset (3x)455 2.19 
Tie-Up/Down   Area  
[µm²]		 Power
[µW/MHz]
TIE0_HVTie-Down to logic Low level36 0.00 
TIE1_HVTie-Up to logic High Level36 0.00 
LOGIC0_HVTie-Down to logic Low level36  0.00 
LOGIC1_HVTie-Up to logic High Level36  0.00 
Majority   Area  
[µm²]		 Power
[µW/MHz]
MAJ31_HVMajority (AB+AC+BC), (1x)109 0.55 
MAJ32_HVMajority (AB+AC+BC), (2x)127 1.00 
Multiplexers   Area  
[µm²]		 Power
[µW/MHz]
MUX21_HV2:1 Multiplexer (1x)109 0.49 
MUX22_HV2:1 Multiplexer (2x)109 0.94 
MUX24_HV2:1 Multiplexer (4x)182 1.62 
MUX26_HV2:1 Multiplexer (6x)182 2.44 
MUX31_HV3:1 Multiplexer (1x)200 0.70 
MUX32_HV3:1 Multiplexer (2x)237 1.33 
MUX33_HV3:1 Multiplexer (3x)291 2.24 
MUX34_HV3:1 Multiplexer (4x)401 3.07 
MUX41_HV4:1 Multiplexer (1x)237 0.68 
MUX42_HV4:1 Multiplexer (2x)273 1.27 
MUX43_HV4:1 Multiplexer (3x)382 2.08 
NAND Gates   Area  
[µm²]		 Power
[µW/MHz]
NAND20_HV2-Input NAND (0.5x)55 0.18 
NAND21_HV2-Input NAND (1x)55 0.35 
NAND22_HV2-Input NAND (2x)55 0.70 
NAND23_HV2-Input NAND (3x)91 1.00 
NAND24_HV2-Input NAND (4x)109 1.38 
NAND26_HV2-Input NAND (6x)164 2.04 
NAND28_HV2-Input NAND (8x)182 2.73 
NAND30_HV3-Input NAND (0.5x)73 0.21 
NAND31_HV3-Input NAND (1x)73 0.41 
NAND32_HV3-Input NAND (2x)127 0.78 
NAND33_HV3-Input NAND (3x)127 1.19 
NAND34_HV3-Input NAND (4x)164 1.59 
NAND40_HV4-Input NAND (0.5x)91 0.24 
NAND41_HV4-Input NAND (1x)91 0.46 
NAND42_HV4-Input NAND (2x)146 1.23 
NAND43_HV4-Input NAND (3x)200 1.84 
NOR Gates   Area  
[µm²]		 Power
[µW/MHz]
NOR20_HV2-Input NOR (0.5x)55 0.22 
NOR21_HV2-Input NOR (1x)55 0.43 
NOR22_HV2-Input NOR (2x)73 0.83 
NOR23_HV2-Input NOR (3x)91 1.20 
NOR24_HV2-Input NOR (4x)109 1.53 
NOR30_HV3-Input NOR (0.5x)73 0.27 
NOR31_HV3-Input NOR (1x)73 0.42 
NOR32_HV3-Input NOR (2x)91 1.07 
NOR33_HV3-Input NOR (3x)127 1.57 
NOR40_HV3-Input NOR (0.5x)73 0.42 
NOR41_HV3-Input NOR (1x)91 0.75 
NOR42_HV3-Input NOR (2x)164 1.51 
OR-AND-INVERT Gates   Area  
[µm²]		 Power
[µW/MHz]
OAI210_HV2-Input OR into 2-Input NAND (0.5x)73 0.25 
OAI211_HV2-Input OR into 2-Input NAND (1x)73 0.49 
OAI212_HV2-Input OR into 2-Input NAND (2x)73 0.98 
OAI2110_HV2-Input OR into 3-Input NAND (0.5x)91 0.26 
OAI2111_HV2-Input OR into 3-Input NAND (1x)91 0.48 
OAI2112_HV2-Input OR into 3-Input NAND (2x)146 0.90 
OAI220_HV2x2-Input OR into 2-Input NAND (0.5x)91 0.21 
OAI221_HV2x2-Input OR into 2-Input NAND (1x)91 0.40 
OAI222_HV2x2-Input OR into 2-Input NAND (2x)91 0.76 
OAI310_HV3-Input OR into 2-Input NAND (0.5x)91 0.33 
OAI311_HV3-Input OR into 2-Input NAND (1x)91 0.62 
OAI312_HV3-Input OR into 2-Input NAND (2x)109 1.18 
Toggle Flip-Flops   Area  
[µm²]		 Power
[µW/MHz]
TFEC1_HVToggle Flip Flop with active high enable and active low clear (1x)346 1.31 
TFEC3_HVToggle Flip Flop with active high enable and active low clear (3x)346 1.98 
TFECP1_HVToggle Flip Flop with active high enable, active low clear and preset (1x)364 1.40 
TFECP3_HVToggle Flip Flop with active high enable, active low clear and preset (3x)364 2.07 
TFEP1_HVToggle Flip Flop with active high enable and active low preset (1x)346 1.31 
TFEP3_HVToggle Flip Flop with active high enable and active low preset (1x)346 1.98 
TFSEC1_HVScan Toggle Flip Flop with active high enable and active low clear (1x)437 1.47 
TFSEC3_HVScan Toggle Flip Flop with active high enable and active low clear (3x)437 2.16 
TFSECP1_HVScan Toggle Flip Flop with active high enable, active low clear and preset (1x)455 1.55 
TFSECP3_HVScan Toggle Flip Flop with active high enable, active low clear and preset (3x)455 2.24 
TFSEP1_HVScan Toggle Flip Flop with active high enable and active low preset (1x)437 1.48 
TFSEP3_HVScan Toggle Flip Flop with active high enable and active low preset (3x)437 2.16 
TFC1_HVToggle Flip Flop with active low clear (1x)291 1.22 
TFC3_HVToggle Flip Flop with active low clear (3x)291 1.88 
TFCP1_HVToggle Flip Flop with active low clear and preset (1x)310 1.30 
TFCP3_HVToggle Flip Flop with active low clear and preset (3x)310 1.97 
TFP1_HVToggle Flip Flop with active low preset (1x)291 1.22 
TFP3_HVToggle Flip Flop with active low preset (3x)291 1.88 
TFSC1_HVScan Toggle Flip Flop with active low clear (1x)346 1.33 
TFSC3_HVScan Toggle Flip Flop with active low clear (3x)364 2.00 
TFSCP1_HVScan Toggle Flip Flop with active low clear and preset (1x)364 1.42 
TFSCP3_HVScan Toggle Flip Flop with active low clear and preset (3x)382 2.08 
TFSP1_HVScan Toggle Flip Flop with active low preset (1x)346 1.33 
TFSP3_HVScan Toggle Flip Flop with active low preset (3x)364 2.00 
XOR Gates   Area  
[µm²]		 Power
[µW/MHz]
XOR20_HV2-input XOR (0.5x)127 0.35 
XOR21_HV2-input XOR (1x)127 0.61 
XOR22_HV2-input XOR (2x)200 1.14 
XOR30_HV3-input XOR (0.5x)200 0.47 
XOR31_HV3-input XOR (1x)200 0.72 
XOR40_HV4-input XOR (0.5x)273 0.49 
XOR41_HV4-input XOR (1x)273 0.79 
XNOR Gates   Area  
[µm²]		 Power
[µW/MHz]
XNR20_HV2-input XNOR (0.5x)109 0.24 
XNR21_HV2-input XNOR (1x)109 0.50 
XNR22_HV2-input XNOR (2x)200 1.03 
XNR30_HV3-input XNOR (0.5x)200 0.58 
XNR31_HV3-input XNOR (1x)200 0.91 
XNR40_HV4-input XNOR (0.5x)273 0.51 
XNR41_HV4-input XNOR (1x)273 0.81 


h35 Cells

 

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