BIST for single port RAM in 0.35µm CMOS (C35/S35)

• Bist Implementation for RAM instances derived from single port RAM compiler (C35/S35)
• Unidirectional / bidirectional RAMs supported
• Bist available for all sizes of  RAM compiler
• Different testalgorithms available
• Is operating on same edge / opposite edge of RAM clock
• "Debuggable" in simulation

• March_C- (10n)
• March LR (14n)
• March CW

Upon customer's specification one of these 3 algorithms is hardwired implemented into the BIST circuit. March CW is available only for unidirectional single port RAM configurations.

Gate Count
Process	all RAM sizes
C35	approx. 900 - 1000 gates

 

• Required customer specification
  • RAM size configuration
  • unidirectional / bidirectional 
  • BIST operating on same/opposite system clock edge
  • test algorithm
     
• Output formats
  • Verilog netlist
  • VHDL netlist

  Upon the specification provided a cell based netlist of the BIST circuit is delivered, based on austriamicrosystems' c35 digital standard cell library (CORELIB). The netlist includes the bist circuit as well as the wrapper to the RAM block. austriamicrosystems' c35 digital standard cell library must be available at customers site.

The faulty clock cycle is monitored by the BIST circuit. The related RAM operation can be reproduced in digital simulation. The faulty cycle data (address, faulty databit) is not stored by the RAM bist circuit.

 

BIST structure generation is an additional service to the generation of RAM instances. Data is provided on a placement of a purchase order.

mailto:ip@austriamicrosystems.com