Metal Programmable ROM16kx8 in 0.35µm CMOS (C35/S35)

 

Key Features
  • Metal programmable ROM 16kx8 in 0.35µm CMOS Process (C35/S35)
  • Synchronous interface / access
  • Single layer programmable (VIA1)
  • Triple metal layout of memory
  • 16k words
  • 8 bit databus
  • Simulation models for 3.3V nominal supply
Deliverables
  • Frontend services
    • CADENCE
      • cell library with symbol, functional, abstract and msps view
      • TLF 3.0 & TLF 4.3 timing data file
      • LEF file for silicon ensemble
      • SDF annotable Verilog model
    • SYNOPSYS
      • cell timing model (interface model)
    • VHDL
      • VITAL95 compliant simulation model
      • TLF timing data file for SDF generation
      • LEF file for silicon ensemble

     

  • Backend Services (on order)
    • CADENCE
      • cell library with additional layout view with reduced layout data (*)
    • gds2 data
      • reduced layout data in gds2 format (*)

    (*) reduced layout data does not contain the following layers:

    • Diffusion
    • Poly1
    • N+ Implant
    • P+ Implant
    • Contact
    The reduced layout data will be replaced with full layout data by austriamicrosystems before production.
Area

Area [mm2]

Process 16k x 8
C35 0.89

Timing
 
Access Time [ns]
Process 16k x 8
C35 4.9

Power consumption

Supply Current [mA/MHz]
Process 2k x 8
C35 0.43

Power and Timing data conditions:
  • typical process parameters
  • VDD = 3.3V
  • Tj = 25C
  • Cload = 1pF
Description
This instance is a VIA1 programmable ROM device. The instance is not included in a HIT-Kit shipment. Memory Simulation models are available on request free of charge, layout data is provided on  placement of a purchase order.
Documentation
Simulation Model
Generation
Please click the link below to download the frontend service package for this metal programmable ROM.

metROM16kx8_frontend.tar.gz