VREG5_2 |
Low Drop 5V-Regulator |
Functional DescriptionVREG5_2 is a highly efficient supply voltage regulator for 5V circuits. It is designed to provide power supply for embedded logic cores as well as external circuits. Fast startup and fast settling on load transients make this cell exceptionally suited for mixed signal ASICs. The high efficiency (load current to quiescent current ratio) is useful for low power applications.The regulator contains a comparator for use as a reset control in digital systems and/or power-down control in analog systems. During the startup time of the regulator the output RESN will stay low until V5V reaches a level of about 4V. Above this threshold RESN goes to high and will remain in this state until V5V goes below a threshold of about 3V. The cell requires a single high supply and generates a 5V supply for on-chip and external subsystems. Input and output voltage are referenced to the negative supply VSSA. Capacitive blocking is recommended to provide current paths for high frequency transients and to prevent oscillations. |
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Key Features
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Pin List
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Electrical Parameters
| Parameter | Symbol | Min | Typ | Max | Unit |
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| Static Parameters | |||||
| Power Supply Range | VDDH | 6.5 | 40 | V | |
| Temperature Range | Temp | -40 | 25 | 85 | °C |
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| Temperature Coefficient of VTEMP |
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| Bias Output Current | IB1µX | 1 | µA | ||
| Bias Output Current |
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| Quiescent Supply Current | IDD | 55 | µA | ||
| Capacitive Load | CL | 0 | 50 | µF | |
| Output Voltage | V5V | 4.5 | 5.0 | 5.5 | V |
| Temperature Coefficient of V5V | TKo | -100 | 10 | 100 | ppm/K |
| Output Current | IOUT | 0 | 10 | mA | |
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(rising slope) Signal RES |
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(falling slope) Signal RES |
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| AC Parameters | |||||
| Power supply rejection ratio | PSSR | dB | |||
| Transient Parameters | |||||
| Startup Time @ IOUT=5mA | Tsup | 5 | µsec | ||







