ADC10 10-Bit Successive Approximation ADC

 

Key Features

  • Full 10-Bit Resolution and Linearity
  • Small Area: 0.417mm²
  • Size: x = 675µm; y = 619µm
  • Supply Voltage: 5V ± 10%
  • Only Single Power Supply Required
  • Internal Sample&Hold

Symbol

 

Description

This Macro Cell is a 10-Bit successive approximation analog to digital converter. The architecture is based on two resistor dividers. The converter operates in free running mode. The conversion is carried out over 11 cycles of the master clock. The conversion range is given by VRP and VRN.

Pin List

Pin Description Capacitance
VIN Input Voltage 9 pF
clock Master Clock 0.1 pF
start Start Of Conversion Signal 0.05 pF
VRP Positive Reference Voltage
VRN Negative Reference Voltage
eoc End Of Conversion
DATA<9:0> Data Output DATA(0) .. LSB

Power Supplies

The converter requires only one power supply (vdd, gnd). The digital part of the converter has been designed to operate from the same supply as the analog part and should cause no disturbance. When using the ADC on a chip with a large portion of digital circuitry, it is recommended to connect the power supplies for the ADC to separate supply pads (the power supply voltages may then be connected externally).
Important: The proper use of blocking capacitors in the application!
It is also possible to split the layout into two parts (analog & digital).

Electrical Parameters

Vsupply: 5V ± 10%
Temperature: 0°C ... 25°C ... 85°C
The maximum error between the ideal and the real transfer curve never exceeds 1 LSB.

Parameter Symbol Min Typ Max Unit
Resolution    10      Bit
Input Voltage Range  Vin  VSS    VDD  V
Differential Nonlinearity  DNL    ± 0.25   LSB *
Integral Nonlinearity  INL   ± 0.5   LSB *
Input Offset Voltage  Vos    ± 0.25   LSB *
Input Impedance  Rin 100     MOhms
Input Capacitance  Cin   9   pF
Reference Impedance  Rref 6.8 8 10.4  kOhms
Power Supply Range  Vdd 4.5 5 5.5  V
Power Supply Current  Idd   0.86    mA
Power Consumption  PVdd   4.3    mW
  Transient Parameters (5V, 25°C)         
Conversion Time  Tc   11   us
Clock Frequency  fc   1   MHz
Clock Duty Cycle  Dc 40   60  %
Settling time of S&H  ts  < 1     µs ** 
* Conditions :VRP = VDD, VRN = VSS, fc = 1MHz, VDD = 5V, temp = 25°C
** 1V step at the input, risetime 1ns, difference 0.5 mV

Output Code Input Voltage
00 0000 0000  VRN....1LSB 
00 0000 0001  1....2LSB 
00 0000 0010  2....3LSB 
..  ... 
11 1111 1111  1023LSB....VRP 
1LSB = (VRP-VRN)/1024

Timing

Continuous Conversion

Setting Start Back To Lo


If you set start back to high again, you will get valid data after 11 cycles again.



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