Voltage and Current Levels for 5.0V/5.0V Nominal Supply Voltage
Junction Temperature Tj = -40 to 125°C
These periphery cells are level shifting periphery cells, which provide 5.0V levels to the core area of the chip and 5.0V levels at the pads of the chip.
Input paths of input and IO level shifting periphery cells
| Type | Cell Name | Vil | Vih | Iil (1) | Iih (2) | Note | ||
|---|---|---|---|---|---|---|---|---|
| min | max | min | max | |||||
| A | ICP_V5 BBC[1-24][P,SP,SMP]_V5(4) | 30% | 70% | NA | -1.0µA | NA | 1.0µA | CMOS (3) |
| B | ICUP_V5 BBCU[1-24][P,SP,SMP]_V5(4) | 30% | 70% | -30µA | -100µA | NA | NA | CMOS w/pullup (3) |
| C | ICDP_V5 BBCD[1-24][P,SP,SMP]_V5(4) | 30% | 70% | NA | NA | 30µA | 100µA | CMOS w/pulldown (3) |
| D | ITP_V5 BBT[1-24][P,SP,SMP]_V5(4) | 0.8V | 2.0V | NA | -1.0µA | NA | 1.0µA | TTL |
| E | ITUP_V5 BBTU[1-24][P,SP,SMP]_V5(4) | 0.8V | 2.0V | -30µA | -100µA | NA | NA | TTL w/pullup |
| F | ITDP_V5 BBTD[1-24][P,SP,SMP]_V5(4) | 0.8V | 2.0V | NA | NA | 30µA | 100µA | TTL w/pulldown |
| FSA | ISP_V5 BBS[1-24][P,SP,SMP]_V5(4) | see below | NA | -1.0µA | NA | 1.0µA | Schmitt Trigger | |
| FSB | ISUP_V5 BBSU[1-24][P,SP,SMP]_V5(4) | see below | -30µA | -100µA | NA | NA | Schmitt Trigger w/pullup | |
| FSC | ISDP_V5 BBSD[1-24][P,SP,SMP]_V5(4) | see below | NA | NA | 30µA | 100µA | Schmitt Trigger w/pulldown | |
| Schmitt Trigger Input Data | ||||
|---|---|---|---|---|
| Type | Characteristics | Conditions | Minimum | Maximum |
| FSA,FSB,FSC | Negative-Going Treshold Vt- | VDD=4.5V VDD=5.5V |
1.62V 2.04V |
1.78V 2.22V |
| Positive-Going Treshold Vt+ | VDD=4.5V VDD=5.5V |
2.72V 3.34V |
2.89V 3.42V |
|
| NOTES: | (1) | Iil is tested at VDD = 5.5V and Vin = 0V |
| (2) | Iih is tested at VDD = 5.5V and Vin = 5.5V | |
| (3) | CMOS input levels are in percentage of VDD | |
| (4) | [1-24] ... output drive strength of a cell in mA. | |
| available: 1mA, 2mA, 4mA, 8mA, 12mA, 16mA, 24mA. | ||
| [P, SP, SMP] ... slew rate control | ||
| P ... no slew rate control. | ||
| SMP ... moderate slew rate control. | ||
| SP ... slew rate control. |
Output paths of output and IO periphery cells
| Type | Cell Name | Vol | Voh | Iol (2) | Ioh (3) | Ioz (4) | Note |
|---|---|---|---|---|---|---|---|
| V | V | mA | mA | µA | |||
| Z | BU[1-24][P,SP,SMP]_V5(5) BB*[1-24][P,SP,SMP]_V5(5) | 0.4 | 4.0 | [1-24](5) | [1-24](5) | NA | CMOS(6) |
| X | BUDU[1-24]P_V5(5) | 0.4 | 4.0 | NA | [1-24](5) | -10 | CMOS(6) open-drain pullup (1) |
| W | BUDD[1-24]P_V5(5) | 0.4 | 4.0 | [1-24](5) | NA | 10 | CMOS(6) open-drain pulldown (1) |
| V | BT[1-24][P,SP,SMP]_V5(5) | 0.4 | 4.0 | [1-24](5) | [1-24](5) | ±10 | CMOS(6) tristate |
| NOTES: | (1) | At test time a 1.5 kOhm resistor is tied to VSS or VDD on open drain device to force a signal level when the device is in a high-impedance state. |
| (2) | Vol, Iol is tested at VDD = 4.5V | |
| (3) | Voh, Ioh is tested at VDD = 4.5V | |
| (4) | Ioz is tested with VDD = 5.5V | |
| (5) | [1-24] ... output drive strength of a cell in mA. | |
| available: 1mA, 2mA, 4mA, 8mA, 12mA, 16mA, 24mA. | ||
| [P, SP, SMP] ... slew rate control | ||
| P ... no slew rate control. | ||
| SMP ... moderate slew rate control. | ||
| SP ... slew rate control. | ||
| (6) | specification covers CMOS and TTL level specification |