Notes
The functions available in the cell libraries are optimized for the usage with synthesis tools.
The Core cells are characterized for 3.3 Volts with nonlinear delays dependent on input slope and output load, which gives timing accuracy similar to a circuit simulator.
Two pad-limited Periphery Cells libraries are available: One for use in pure 3.3V systems and one for mixed 3.3V/5V systems.
The 3.3V / 5V library provides level shifting capabilities for 5V I/O and 3.3V Core operation and requires separate supply voltages at both 3.3V and 5V.
The digital standard cell databook contains logic and timing information, cell area and a brief description.
Power consumption figures for all cells are calculated under the following conditions:
Input slope = 1ns
Output load = 20 fF * drive strength for the core cells.
Output load = 2.5 pF * drive strength for the periphery cells.
The applied testpattern for power calculation covers all possible input combinations for combinatorial cells and therefore provides an averaging of power for all possible input patterns. Sequential cells are related to their clock-input signal. The values are given in µW and are related to a 1MHz toggling frequency. For other frequencies the given number must be linearly scaled.
Modelling of Pull-Up/Pull-Down I/O Cells
When I/O cells with Pull-up or Pull-down function (e.g. BBCUxP and BBCDxP) are used in input mode with a high-impedance signal on the PAD pin they will always generate a logical 1 (pull-up) or logical 0 (pull-down) at the internal Y pin. This situation is however modelled in our Verilog and VHDL simulation with an X state at the output, this is shown in the truth-tables provided.
Definition of Rise/Fall Times
For all cells the following output transitions are defined as "Rise" or "Fall". The transitions to/from a high-impedance "Z" state are only used for tri-state cells (e.g. BTx, ITx, BTxP, BUDDxP and BUDUxP).
|
Rise |
Fall |
|---|---|
|
0 -> 1 |
1 -> 0 |
|
Z -> 1 |
Z -> 0 |
|
0 -> Z |
1 -> Z |
Interpreting "Negative Delays"
Under certain conditions, delay calculations may result in negative delay values.
These ‘negative delays’ are mainly caused by the difference between timing acquisition and the physical cell threshold as shown in the drawing below.
Note: Negative delays are set to "0" by some simulation tools.
Related Documents / Revisions
|
Rev. |
Date |
Related Documents / Comments |
|---|---|---|
|
1.0 |
Sep 2002 |
Release of C35 CORELIB Databook. |
|
1.1 |
Jan 2003 |
Updated Min. Width values for C, RN, SN in all D-type, JK and Toggle Flip Flops as well as GN, RN, SN in all D-Latches. |
|
1.2 |
May 2003 |
Updated Setup/Hold & Min.Width values. |
| 2.0 | May 2004 |
HTML based, modified power. |