c35 Cells

 

c35 Core Cells by Name

Notes

Half Adders   Area  
[µm²]
Power
[µW/MHz]
ADD21Half-Adder (1x)146 0.91 
ADD22Half-Adder (2x)146 1.75 
Full Adders   Area  
[µm²]
Power
[µW/MHz]
ADD31Full-Adder (1x)273 1.13 
ADD32Full-Adder (2x)273 2.10 
AND-OR-INVERT Gates   Area  
[µm²]
Power
[µW/MHz]
AOI2102-Input AND into 2-Input NOR (0.5x)73 0.26 
AOI2112-Input AND into 2-Input NOR (1x)73 0.49 
AOI2122-Input AND into 2-Input NOR (2x)91 0.90 
AOI21102-Input AND into 3-Input NOR (0.5x)91 0.35 
AOI21112-Input AND into 3-Input NOR (1x)91 0.66 
AOI21122-Input AND into 3-Input NOR (2x)127 1.19 
AOI2202x2-Input AND into 2-Input NOR (0.5x)91 0.33 
AOI2212x2-Input AND into 2-Input NOR (1x)91 0.60 
AOI2222x2-Input AND into 2-Input NOR (2x)109 1.10 
AOI3103-Input AND into 2-Input NOR (0.5x)91 0.32 
AOI3113-Input AND into 2-Input NOR (1x)91 0.62 
AOI3123-Input AND into 2-Input NOR (2x)109 1.18 
Tri-State Buffers   Area  
[µm²]
Power
[µW/MHz]
BUFE2Tri-State Buffer with active high enable (2x)146 0.84 
BUFE4Tri-State Buffer with active high enable (4x)164 1.59 
BUFE6Tri-State Buffer with active high enable (6x)182 2.28 
BUFE8Tri-State Buffer with active high enable (8x)255 3.14 
BUFE10Tri-State Buffer with active high enable (10x)273 3.83 
BUFE12Tri-State Buffer with active high enable (12x)328 4.54 
BUFE15Tri-State Buffer with active high enable (15x)364 5.67 
Tri-State Buffers   Area  
[µm²]
Power
[µW/MHz]
BUFT2Tri-State Buffer with active low enable (2x)146 0.83 
BUFT4Tri-State Buffer with active low enable (4x)164 1.59 
BUFT6Tri-State Buffer with active low enable (6x)182 2.29 
BUFT8Tri-State Buffer with active low enable (8x)255 3.13 
BUFT10Tri-State Buffer with active low enable (10x)273 3.84 
BUFT12Tri-State Buffer with active low enable (12x)328 4.54 
BUFT15Tri-State Buffer with active low enable (15x)364 5.67 
Buffers   Area  
[µm²]
Power
[µW/MHz]
BUF2Buffer (2x)55 0.84 
BUF4Buffer (4x)73 1.60 
BUF6Buffer (6x)73 2.36 
BUF8Buffer (8x)91 3.22 
BUF12Buffer (12x)109 4.67 
BUF15Buffer (15x)146 5.95 
Bus Holder   Area  
[µm²]
Power
[µW/MHz]
BUSHDBusholder55 0.00 
Clock Buffers   Area  
[µm²]
Power
[µW/MHz]
CLKBU2Symmetrical Buffer for clock tree synthesis (2x)55 0.72 
CLKBU4Symmetrical Buffer for clock tree synthesis (4x)73 1.37 
CLKBU6Symmetrical Buffer for clock tree synthesis (6x)73 2.00 
CLKBU8Symmetrical Buffer for clock tree synthesis (8x)91 2.93 
CLKBU12Symmetrical Buffer for clock tree synthesis (12x)109 4.20 
CLKBU15Symmetrical Buffer for clock tree synthesis (15x)146 5.24 
Clock Gating Cells   Area  
[µm²]
Power
[µW/MHz]
DLSG1Clock gating cell 219 0.8 
Clock Inverters   Area  
[µm²]
Power
[µW/MHz]
CLKIN0Symmetrical Inverter for clock tree synthesis (0.5x)36 0.17 
CLKIN1Symmetrical Inverter for clock tree synthesis (1x)36 0.32 
CLKIN2Symmetrical Inverter for clock tree synthesis (2x)36 0.63 
CLKIN3Symmetrical Inverter for clock tree synthesis (3x)36 0.94 
CLKIN4Symmetrical Inverter for clock tree synthesis (4x)55 1.21 
CLKIN6Symmetrical Inverter for clock tree synthesis (6x)55 1.79 
CLKIN8Symmetrical Inverter for clock tree synthesis (8x)73 2.46 
CLKIN10Symmetrical Inverter for clock tree synthesis (10x)91 3.02 
CLKIN12Symmetrical Inverter for clock tree synthesis (12x)91 3.61 
CLKIN15Symmetrical Inverter for clock tree synthesis (15x)109 4.54 
D-Type Flip-Flops   Area  
[µm²]
Power
[µW/MHz]
DF1D-Type Flip Flop (1x)273 1.14 
DF3D-Type Flip Flop (3x)273 1.80 
DFC1D-Type Flip Flop with active low clear (1x)310 1.22 
DFC3D-Type Flip Flop with active low clear (3x)310 1.88 
DFCP1D-Type Flip Flop with active low clear and preset (1x)328 1.31 
DFCP3D-Type Flip Flop with active low clear and preset (3x)328 1.97 
DFP1D-Type Flip Flop with active low preset (1x)310 1.21 
DFP3D-Type Flip Flop with active low preset (3x)310 1.89 
DFS1Scan D-Type Flip Flop (1x)364 1.27 
DFS3Scan D-Type Flip Flop (3x)382 1.92 
DFSC1Scan D-Type Flip Flop with active low clear (1x)382 1.36 
DFSC3Scan D-Type Flip Flop with active low clear (3x)401 2.02 
DFSCP1Scan D-Type Flip Flop with active low clear and preset (1x)401 1.46 
DFSCP3Scan D-Type Flip Flop with active low clear and preset (3x)419 2.11 
DFSP1Scan D-Type Flip Flop with active low preset (1x)382 1.36 
DFSP3Scan D-Type Flip Flop with active low preset (3x)401 2.02 
DFE1D-Type Flip Flop with active high enable (1x)328 1.33 
DFE3D-Type Flip Flop with active high enable (3x)346 1.98 
DFEC1D-Type Flip Flop with active high enable and active low clear (1x)346 1.41 
DFEC3D-Type Flip Flop with active high enable and active low clear (3x)364 2.06 
DFECP1D-Type Flip Flop with active high enable, active low clear and preset (1x)382 1.49 
DFECP3D-Type Flip Flop with active high enable, active low clear and preset (3x)401 2.15 
DFEP1D-Type Flip Flop with active high enable and active low preset (1x)346 1.40 
DFEP3D-Type Flip Flop with active high enable and active low preset (3x)364 2.05 
DFSE1Scan D-Type Flip Flop with active high enable (1x)419 1.42 
DFSE3Scan D-Type Flip Flop with active high enable (3x)437 2.08 
DFSEC1Scan D-Type Flip Flop with active high enable and active low clear (1x)437 1.50 
DFSEC3Scan D-Type Flip Flop with active high enable and active low clear (3x)455 2.16 
DFSECP1Scan D-Type Flip Flop with active high enable, active low clear and preset (1x)455 1.59 
DFSECP3Scan D-Type Flip Flop with active high enable, active low clear and preset (3x)473 2.25 
DFSEP1Scan D-Type Flip Flop with active high enable and active low preset (1x)437 1.50 
DFSEP3Scan D-Type Flip Flop with active high enable and active low preset (3x)455 2.16 
Data Latches   Area  
[µm²]
Power
[µW/MHz]
DL1Data Latch (1x)200 1.22 
DL3Data Latch (3x)200 2.55 
DLC1Data Latch with active low clear (1x)219 1.36 
DLC3Data Latch with active low clear (3x)219 2.68 
DLCP1Data Latch with active low clear and preset (1x)237 1.45 
DLCP3Data Latch with active low clear and preset (3x)237 2.78 
DLP1Data Latch with active low preset (1x)200 1.30 
DLP3Data Latch with active low preset (3x)200 2.64 
DLQ1Data Latch with Q-output only (1x)182 0.33 
DLQ3Data Latch with Q-output only (3x)182 0.39 
DLCQ1Data Latch with Q-output only and active low clear (1x)182 1.12 
DLCQ3Data Latch with Q-output only and active low clear (3x)182 1.95 
DLCPQ1Data Latch with Q-output only, active low clear and preset (1x)200 0.53 
DLCPQ3Data Latch with Q-output only, active low clear and preset (3x)200 1.17 
DLPQ1Data Latch with Q-output only and active low preset (1x)182 0.94 
DLPQ3Data Latch with Q-output only and active low preset (3x)182 1.59 
Delay Buffers   Area  
[µm²]
Power
[µW/MHz]
DLY12Single Delay (2x)164 1.74 
DLY22Double Delay (2x)219 2.65 
DLY32Triple Delay (2x)310 3.45 
DLY42Quadr. Delay (2x)401 4.41 
Inverting Majority   Area  
[µm²]
Power
[µW/MHz]
IMAJ30Inverting Majority ~(AB+AC+BC), (0.5x)109 0.27 
IMAJ31Inverting Majority ~(AB+AC+BC), (1x)109 0.53 
Inverting Multiplexers   Area  
[µm²]
Power
[µW/MHz]
IMUX20Inverting 2:1 Multiplexer (0.5x)91 0.25 
IMUX21Inverting 2:1 Multiplexer (1x)91 0.48 
IMUX22Inverting 2:1 Multiplexer (2x)146 0.93 
IMUX23Inverting 2:1 Multiplexer (3x)146 1.15 
IMUX24Inverting 2:1 Multiplexer (4x)182 1.71 
IMUX30Inverting 3:1 Multiplexer (0.5x)182 0.46 
IMUX31Inverting 3:1 Multiplexer (1x)219 0.87 
IMUX32Inverting 3:1 Multiplexer (2x)237 1.52 
IMUX33Inverting 3:1 Multiplexer (3x)364 2.41 
IMUX40Inverting 4:1 Multiplexer (0.5x)219 0.44 
IMUX41Inverting 4:1 Multiplexer (1x)255 0.86 
IMUX42Inverting 4:1 Multiplexer (2x)364 1.56 
Inverters   Area  
[µm²]
Power
[µW/MHz]
INV0Inverter (0.5x)36 0.17 
INV1Inverter (1x)36 0.34 
INV2Inverter (2x)36 0.65 
INV3Inverter (3x)36 0.96 
INV4Inverter (4x)55 1.24 
INV6Inverter (6x)55 1.84 
INV8Inverter (8x)73 2.52 
INV10Inverter (10x)91 3.09 
INV12Inverter (12x)91 3.71 
INV15Inverter (15x)109 4.67 
JK Flip-Flops   Area  
[µm²]
Power
[µW/MHz]
JK1JK Flip-Flop (1x)346 1.29 
JK3JK Flip-Flop (3x)346 1.96 
JKC1JK Flip-Flop with active low clear (1x)364 1.38 
JKC3JK Flip-Flop with active low clear (3x)364 2.04 
JKCP1JK Flip-Flop with active low clear and preset (1x)382 1.46 
JKCP3JK Flip-Flop with active low clear and preset (3x)382 2.12 
JKP1JK Flip-Flop with active low preset (1x)364 1.38 
JKP3JK Flip-Flop with active low preset (3x)364 2.04 
JKS1Scan JK Flip-Flop (1x)437 1.45 
JKS3Scan JK Flip-Flop (3x)437 2.10 
JKSC1Scan JK Flip-Flop with active low clear (1x)455 1.53 
JKSC3Scan JK Flip-Flop with active low clear (3x)455 2.19 
JKSCP1Scan JK Flip-Flop with active low clear and preset (1x)473 1.61 
JKSCP3Scan JK Flip-Flop with active low clear and preset (3x)473 2.27 
JKSP1Scan JK Flip-Flop with active low preset (1x)455 1.53 
JKSP3Scan JK Flip-Flop with active low preset (3x)455 2.19 
Tie-Up/Down   Area  
[µm²]
Power
[µW/MHz]
TIE0Tie-Down to logic Low level36 0.00 
TIE1Tie-Up to logic High Level36 0.00 
LOGIC0Tie-Down to logic Low level36 0.00 
LOGIC1Tie-Up to logic High Level36 0.00 
Majority   Area  
[µm²]
Power
[µW/MHz]
MAJ31Majority (AB+AC+BC), (1x)109 0.55 
MAJ32Majority (AB+AC+BC), (2x)127 1.00 
Multiplexers   Area  
[µm²]
Power
[µW/MHz]
MUX212:1 Multiplexer (1x)109 0.49 
MUX222:1 Multiplexer (2x)109 0.94 
MUX242:1 Multiplexer (4x)182 1.62 
MUX262:1 Multiplexer (6x)182 2.44 
MUX313:1 Multiplexer (1x)200 0.70 
MUX323:1 Multiplexer (2x)237 1.33 
MUX333:1 Multiplexer (3x)291 2.24 
MUX343:1 Multiplexer (4x)401 3.07 
MUX414:1 Multiplexer (1x)237 0.68 
MUX424:1 Multiplexer (2x)273 1.27 
MUX434:1 Multiplexer (3x)382 2.08 
NAND Gates   Area  
[µm²]
Power
[µW/MHz]
NAND202-Input NAND (0.5x)55 0.18 
NAND212-Input NAND (1x)55 0.35 
NAND222-Input NAND (2x)55 0.70 
NAND232-Input NAND (3x)91 1.00 
NAND242-Input NAND (4x)109 1.38 
NAND262-Input NAND (6x)164 2.04 
NAND282-Input NAND (8x)182 2.73 
NAND303-Input NAND (0.5x)73 0.21 
NAND313-Input NAND (1x)73 0.41 
NAND323-Input NAND (2x)127 0.78 
NAND333-Input NAND (3x)127 1.19 
NAND343-Input NAND (4x)164 1.59 
NAND404-Input NAND (0.5x)91 0.24 
NAND414-Input NAND (1x)91 0.46 
NAND424-Input NAND (2x)146 1.23 
NAND434-Input NAND (3x)200 1.84 
NOR Gates   Area  
[µm²]
Power
[µW/MHz]
NOR202-Input NOR (0.5x)55 0.22 
NOR212-Input NOR (1x)55 0.43 
NOR222-Input NOR (2x)73 0.83 
NOR232-Input NOR (3x)91 1.20 
NOR242-Input NOR (4x)109 1.53 
NOR303-Input NOR (0.5x)73 0.27 
NOR313-Input NOR (1x)73 0.42 
NOR323-Input NOR (2x)91 1.07 
NOR333-Input NOR (3x)127 1.57 
NOR403-Input NOR (0.5x)73 0.42 
NOR413-Input NOR (1x)91 0.75 
NOR423-Input NOR (2x)164 1.51 
OR-AND-INVERT Gates   Area  
[µm²]
Power
[µW/MHz]
OAI2102-Input OR into 2-Input NAND (0.5x)73 0.25 
OAI2112-Input OR into 2-Input NAND (1x)73 0.49 
OAI2122-Input OR into 2-Input NAND (2x)73 0.98 
OAI21102-Input OR into 3-Input NAND (0.5x)91 0.26 
OAI21112-Input OR into 3-Input NAND (1x)91 0.48 
OAI21122-Input OR into 3-Input NAND (2x)146 0.90 
OAI2202x2-Input OR into 2-Input NAND (0.5x)91 0.21 
OAI2212x2-Input OR into 2-Input NAND (1x)91 0.40 
OAI2222x2-Input OR into 2-Input NAND (2x)91 0.76 
OAI3103-Input OR into 2-Input NAND (0.5x)91 0.33 
OAI3113-Input OR into 2-Input NAND (1x)91 0.62 
OAI3123-Input OR into 2-Input NAND (2x)109 1.18 
Toggle Flip-Flops   Area  
[µm²]
Power
[µW/MHz]
TFEC1Toggle Flip Flop with active high enable and active low clear (1x)346 1.31 
TFEC3Toggle Flip Flop with active high enable and active low clear (3x)346 1.98 
TFECP1Toggle Flip Flop with active high enable, active low clear and preset (1x)364 1.40 
TFECP3Toggle Flip Flop with active high enable, active low clear and preset (3x)364 2.07 
TFEP1Toggle Flip Flop with active high enable and active low preset (1x)346 1.31 
TFEP3Toggle Flip Flop with active high enable and active low preset (1x)346 1.98 
TFSEC1Scan Toggle Flip Flop with active high enable and active low clear (1x)437 1.47 
TFSEC3Scan Toggle Flip Flop with active high enable and active low clear (3x)437 2.16 
TFSECP1Scan Toggle Flip Flop with active high enable, active low clear and preset (1x)455 1.55 
TFSECP3Scan Toggle Flip Flop with active high enable, active low clear and preset (3x)455 2.24 
TFSEP1Scan Toggle Flip Flop with active high enable and active low preset (1x)437 1.48 
TFSEP3Scan Toggle Flip Flop with active high enable and active low preset (3x)437 2.16 
TFC1Toggle Flip Flop with active low clear (1x)291 1.22 
TFC3Toggle Flip Flop with active low clear (3x)291 1.88 
TFCP1Toggle Flip Flop with active low clear and preset (1x)310 1.30 
TFCP3Toggle Flip Flop with active low clear and preset (3x)310 1.97 
TFP1Toggle Flip Flop with active low preset (1x)291 1.22 
TFP3Toggle Flip Flop with active low preset (3x)291 1.88 
TFSC1Scan Toggle Flip Flop with active low clear (1x)346 1.33 
TFSC3Scan Toggle Flip Flop with active low clear (3x)364 2.00 
TFSCP1Scan Toggle Flip Flop with active low clear and preset (1x)364 1.42 
TFSCP3Scan Toggle Flip Flop with active low clear and preset (3x)382 2.08 
TFSP1Scan Toggle Flip Flop with active low preset (1x)346 1.33 
TFSP3Scan Toggle Flip Flop with active low preset (3x)364 2.00 
XOR Gates   Area  
[µm²]
Power
[µW/MHz]
XOR202-input XOR (0.5x)127 0.35 
XOR212-input XOR (1x)127 0.61 
XOR222-input XOR (2x)200 1.14 
XOR303-input XOR (0.5x)200 0.47 
XOR313-input XOR (1x)200 0.72 
XOR404-input XOR (0.5x)273 0.49 
XOR414-input XOR (1x)273 0.79 
XNOR Gates   Area  
[µm²]
Power
[µW/MHz]
XNR202-input XNOR (0.5x)109 0.24 
XNR212-input XNOR (1x)109 0.50 
XNR222-input XNOR (2x)200 1.03 
XNR303-input XNOR (0.5x)200 0.58 
XNR313-input XNOR (1x)200 0.91 
XNR404-input XNOR (0.5x)273 0.51 
XNR414-input XNOR (1x)273 0.81 


c35 Cells